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JVC RX-E100RSL Service Manual page 10

Audio/video control receiver
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RX-E100RSL/RX-E100RSB
Pin function (2/2)
No.
Pin name
I/O
19
NC
20
ADIF
21
CAD1
22
CAD0
LOUT3
23
O
24
ROUT3
O
25
LOUT2
O
26
ROUT2
O
27
LOUT1
O
28
ROUT1
O
29
LIN-
30
LIN+
RIN-
31
32
RIN+
33
DZF2
O
OVF
O
34
VCOM
O
35
VREFH
36
AVDD
37
AVSS
38
DZF1
O
39
MCLK
40
P/S
41
DIF0
CSN
42
DIF1
SCL/CCLK
43
LOOP0
SAD/CDTI
I/O
LOOP1
44
Notes : 1. SDOS, SMUTE, DFS, and LOOP1 pins are ORed with register data if P/S = "L".
2. The group 1 and 2 can be selected by DZFM2-0 bit if P/S = "L" and DZFME = "L".
3. This pin becomes OVF pin if OVFE bit is set to "1" at serial control mode.
4. All input pins should not be left floating.
1-10
No Connect
Function
No internal bonding.
-
Analog Input Format Select Pin
"H" : Full-differential input, "L" : Single-ended input
I
Chip Address 1 Pin
Chip Address 0 Pin
I
DAC3 Lch Analog Output Pin
I
DAC3 Rch Analog Output Pin
DAC2 Lch Analog Output Pin
DAC2 Rch Analog Output Pin
DAC1 Lch Analog Output Pin
DAC1 Rch Analog Output Pin
Lch Analog Negative Input Pin
Lch Analog Positive Input Pin
I
Rch Analog Negative Input Pin
I
Rch Analog Positive Input Pin
I
Zero Input Detect 2 Pin (Note 2)
I
When the input data of the group 1 follow total 8192LRCK cycles with "0" input data,
this pin goes to "H".
Analog Input Overflow Detect Pin (Note 3)
This pin goes to "H" if the analog input of Lch or Rch is overflows.
Common Voltage Output Pin,AVDD/2
Large external capacitor around 2.2uF is used to reduce power-supply noise.
Positive Voltage Reference Input Pin,AVDD
Analog Power Supply Pin,4.5V~5.5V
I
Analog Ground Pin,0V
-
Zero Input Detect 1 Pin (Note 2)
-
When the input data of the group 1 follow total 8192 LRCK cycles with "0" input data,
this pin goes to "H".
Master Clock Input Pin
Parallel / Serial Select Pin
I
"L" : Serial control mode, "H" : Parallel control mode
I
Audio Data Interface Format 0 Pin in parallel mode
Chip select pin in 3-wire serial control mode
I
This pin should be connected to DVDD at I2C bus control mode
I
Audio Data Interface Format 1 Pin in parallel mode
Control Data Clock Pin in serial control mode
I
I2C = "L" : CCLK(3-wire Serial), I2C = "H" : SCL(I2CBus)
I
Loopback Mode 0 Pin in parallel control mode
Enables digital loop-back from ADC to 3 DACs.
I
Control Data Input Pin in serial control mode
I2C = "L" : CDTI(3-wire Serial), I2C = "H" : SDA(I2CBus)
Loopback Mode 1 Pin (Note 1)
Enable all 3 DAC channels to be input from SDTII.
I
AK4527(1/2)

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