Output Timing Specifications - Hamamatsu Photonics C11440-10C Instruction Manual

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OUTPUT TIMING SPECIFICATIONS

① Pixel Timing at 1x1 (12 bit 2TAP output)
TxCLK 74.25 MHz
DVALID
DATA (TAP1)
DATA (TAP2)
HVALID
VVALID
1) DVALID output is high all the time
2) HVALID changes synchronizing with falling edge of TxCLK
3) VVALID changes synchronizing with falling edge of TxCLK
4) DATA will be valid with rising edge of TxCLK
② Pixel Timing at 2x2 (14 bit output)
TxCLK 74.25 MHz
DVALID
DATA
HVALID
VVALID
1) DVALID is valid at High
2) HVALID changes synchronizing with falling edge of TxCLK
3) VVALID changes synchronizing with falling edge of TxCLK
4) DATA will be valid with rising edge of TxCLK when DVALID is H.
1 2 3 4
961 961 961 961
1 2 3 4
C11440-10C Ver.1.2
958 959 960
1918 1919 1920
958 959 960
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