Denon DN-X400 Service Manual page 11

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SM5902AF (Main unit: IC302)
SHOCK PROOF MEMORY CONTROLLER
SM5902AF Terminal Function
Pin No. Symbol
1 V 2
DD
2 UC1
3 UC2
4 UC3
5 UC4
6 UC5
7 DIT
8 NTEST
9 CLK
10 Vss
11 YSRDATA
12 YLRCK
TE
L 13942296513
13 YSCK
14 ZSCK
15 ZLRCK
16 ZSRDATA
17 YFLAG
18 YFCLK
19 YBLKCK
20 NRESET
21 ZSENSE
22 V 1
DD
23 YDMUTE
24 YMLD
25 YMDATA
26 YMCLK
27 A10
28 NCAS
29 D2
30 D3
31 D0
32 D1
33 NWE
34 NRAS
35 A9
36 A8
37 A7
www
38 A6
39 A5
40 A4
.
41 A0
42 A1
43 A2
44 A3
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44
I/O

V power supply terminal.
DD
IP/O Microcomputer interface extended I/O 1. Not Used (OPEN)
IP/O Microcomputer interface extended I/O 2. Not Used (OPEN)
IP/O Microcomputer interface extended I/O 3. Not Used (OPEN)
IP/O Microcomputer interface extended I/O 4. Not Used (OPEN)
IP/O Microcomputer interface extended I/O 5. Not Used (OPEN)
O Digital audio interface terminal.
IP Test terminal.
I 16.9344 MHz clock input.

Ground terminal.
I Audio serial input data.
I Audio serial input LR clock.
I Audio serial input bit clock.
O Audio serial output bit clock.
O Audio serial output LR clock.
O Audio serial output data.
I RAM overflow flag for signal processing IC.
I X'tal system frame clock.
I Sub-code block clock signal.
I System reset terminal.
O Microcomputer interface status output.

V power supply terminal.
DD
I Forcible mute terminal.
I Microcomputer interface latch clock.
I Microcomputer interface serial data.
I Microcomputer interface shift clock.
O DRAM address 10.
O DRAM CAS control.
I/O DRAM data input/output 2.
I/O DRAM data input/output 3.
I/O DRAM data input/output 0.
I/O DRAM data input/output 1.
O DRAM WE control.
O DRAM RAS control.
O DRAM address 9.
O DRAM address 8.
O DRAM address 7.
O DRAM address 6.
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O DRAM address 5.
y
O DRAM address 4.
i
O DRAM address 0.
O DRAM address 1.
O DRAM address 2.
O DRAM address 3.
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2 9
8
33
23
22
12
1 11
Function
Q Q
3 6 7 1 3 1 5
co
.
DN-X400
9 4 2 8
Setting
H
Lch
0 5 8 2 9 9 4 2 8
Lch
Mute
m
9 9
L
Test
Rch
9 9
Rch
Over
Reset
11