Intel LP300 Service Manual page 69

Schematic Diagrams
Clock Generator
Sheet 2 of 32
CLK GEN
ICH48CLK
SIO48MHZ
[2] CLKREF2
[2] CLKREF1
[5] MCH66IN
ICH66CLK
[9] ATI66CLK
+3VCLK
+3VCLK
B - 4 Mainboard (71-P3000-004A)
+3VCLK
L10 1 2 0_1206
+3V
R322 1 2 4.7K
+3V
R309 1 2 4.7K
+3V
[7,15,22] SMBDATA
[7,15,22] SMBCLK
Z0102 1 2 Z0101
R45 0
1 2 Z0103
C73 Y1 C90
14.318MHZ
C506 C507 C531 C529 5P 5P
10P 10P *C *C
R321 1 2 33 FS0
R318 1 2 33 FS1
R67 1 2 33 3VMREF_B
R64 1 2 33 3VMREF
R65 1 2 33 3V66_3
R68 1 2 33 3V66_2
R58 1 2 33 3V66_1
3V66_0
T3
C530 C533 C532
10P 10P 10P
[16,23,26] SUSB#
Z0104
R57
475_1%
Iref=2.32mA
C89 C69 C92 C93 C97 C98 C94
10U/10V 4.7U/10V 0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R
C58 C64 C99 C57 C60 C59 C62
0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R 0.1U_X7R
0.5" MAX
U7
4 8 PCICLK0 R312 1 2 33
VDD1 PCICLK0
10
VDD2
16 9 PCICLK1 R313 1 2 33
VDD3 PCICLK1
22
VDD4
27 11 PCICLK2 R314 1 2 33
VDD5 PCICLK2
29
VDD6
36 12 PCICLK3 R320 1 2 33
VDD7 PCICLK3
38
VDD8
43 14 PCICLK4 R315 1 2 33
VDD9 PCICLK4
49
VDD10
56 15 PCICLK5 R316 1 2 33
VDD11 PCICLK5
23 17 PCICLK6
SDATA PCICLK6 T490
18 FS2 R36 1 2 10K
PCICLK7/FS2
52
SCLK
20 FS3 R306 1 2 10K
PCICLK8/FS3
5 21 SEL100/133 R308 1 2 *R
X1 PCICLK9/SEL100/133 +3VCLK
R307 1 2 470
LOW FOR 100MHZ OPERATION
6 2 MSEL0 R319 1 2 33
X2 MULTSEL0/REF0
3 MSEL1
MULTSEL1REF1
0.5" MAX
25
FS0/48MHZ_0
42 CPUCLKT0 R60 1 2 33
CPUCLKT0
26 45 CPUCLKT1 R61 1 2 33
FS1/48MHZ_1 CPUCLKT1
48 CPUCLKT2 R63 1 2 33
CPUCLKT2
51 CPUCLKT3
CPUCLKT3 T1
54
3VMREF_B
41 CPUCLKC0 R59 1 2 33
CPUCLKC0
55 44 CPUCLKC1 R66 1 2 33
3VMREF CPUCLKC1
47 CPUCLKC2 R62 1 2 33
CPUCLKC2
50 CPUCLKC3
CPUCLKC3 T2
35
3V66_3
34
3V66_2
31 1 R to Node:
3V66_1 GND1
30 7
0.2" MAX
3V66_0 GND2
13
GND3
19
GND4
24
GND5
32
GND6
33
GND7
37
GND8
28 40
PD# GND9
46
GND10
39 53
IREF GND11
CLOCK NOTICE:
Spacing to other traces: 25mils
ICS9250-37
Line width: 7.0mils
FS0 R311 1
R695 1
R697 1
FS1 R39 1
C95 C96
FS1 FS0 CPU PCI
0.1U_X7R 0.1U_X7R
0 1 100.00 33.33
C61
0.1U_X7R
ICH2PCLK
FWHCLK [15]
LANPCLK
CBPCLK [19]
MINIPCICLK
SIOPCLK
C499 C500 C501 C502 C503 C504
10P 10P 10P 10P 10P 10P
ICH14CLK [15]
C498 1 2 *C
CPUCLK [4]
ITPCLK [4]
MCHCLK [5]
CPUCLK# [4]
ITPCLK# [4]
MCHCLK# [5]
0-0.2 inches
Node to chip:
12" MAX
R335 R339 R338 R334 R336 R337
51_1% 51_1% 51_1% 51_1% 51_1% 51_1%
2 10K MSEL1 R666 1 2 10K
+3VCLK +3VCLK
2 *10K R696 1 2 *10K
2 *10K R698 1 2 *10K
2 10K MSEL0 R665 1 2 10K
3V66
66.67
+3V [3,10,11,13,14,26,27,28,31]