Analog Devices Blackfin Getting Started page 15

Figure 1-1 shows a block diagram of a single core ADSP-BF533 Blackfin
16/32-bit processor.
VOLTAGE
JTAG
REGULATOR
B
CORE
80KB
INST
.
SRAM / CACHE
SPORT0 SPORT1
Figure 1-1. Single Core ADSP-BF533 Blackfin 16/32-Bit Processor
Blackfin processors support both protected and unprotected operating
modes that prevent users from accessing or affecting shared parts of the
system. In addition, the processors provide memory management capabil-
ities that enable users to define separate application development spaces.
This design feature prevents distinct code sections from being overwritten.
At the same time, the Blackfin architecture allows asynchronous interrupts
Getting Started With Blackfin Processors
SYSTEM CONTROL BLOCKS
EVENT WATCHDOG
CONTROLLER TIMER
64KB
DATA
SYSTEM INTERFACE UNIT
UART
TIMERS
SPI
IrDA
(3)
MEMORY REAL TIME
PLL
DMA CLOCK
L1 MEMORY
PERIPHERAL
BLOCKS
Introduction
16-BIT
EXTERNAL
BUS
INTERFACE
HIGH SPEED I/O
PPI/GPIO
1-3