XFX PM102 C51 Installation Manual page 55

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Chapter 4: Raid Setup and LED Error Codes
Code(hex)
C0
C1
C2
C3
C4
C5
C6
CF
Code(hex)
F0
F1
F2
F3
00
01
04
08
0C
10
20
30
40
44
48
4C
50
54
FE
FF
Name
Base CPU test
Memory Presence
Early Memory
Extend Memory
Special Display
Early Shadow
Cache presence
CMOS Check
Nvidia Added POST Codes
Name
HW Ident
SLAM Table
Early SLAM table
Init Com Port
HW Init
Override Parameters
Process SPD
Query HW
Load ROM Table
Init Memory Controller
Init PCI Express
Init Spread Spectrum
Set Top-Of-Memory
Late SLAM table
Previous Power State
SLAM table
Hardware Workarounds
NVMM
NV Memory Test
ERROR handler
Boot
Description
Read/Write CPU registers
Base memory detect
Board Initialization
Turn on extended memory, cache initialization
First display initialization
Early shadow enable for fast boot
External cache size detection
CMOS checkup
Description
Identify HW in the system
Register the slam tables
Early SLAM table
COM port initialization
Initialize hardware devices
Override input parameters etc. before QUERY
Read SPD & fill in arrays
Query the hardware devices
ROM table pointer
Initialize the Memory Controller
PCI Express Initialization
Load Spread Spectrum tables
Set Top-Of-Memory registers
Late SLAM table
Previous Power State SLAM table
Hardware Workarounds
Restore, and exit NVMM
NV Memory Test
ERROR handler
53

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