Analog Devices VISUALDSP++ 3.5 Manual page 145

Fractional data has a representation similar to that of integers except that
while an integer value is considered to have a decimal point to the right of
the least significant bit, a fractional value is considered to have a decimal
point to the left of the most significant bit. Fractional values are usually
held in 16-bit or 32-bit "containers". In each case, signed values are in the
range [-1.0, +1.0).
The bit operations on fractional data are identical to those on integer data,
but there are three aspects of the result that are normally treated
differently:
1. MSB extraction. Multiplication is a widening operation, thus mul-
tiplying a 16-bit value by another 16-bit value produces a 32-bit
result. If a 16-bit integer result is required then this is taken to be
the least significant 16 bits of the result, and the upper 16 bits are
regarded as overflow. For a fractional operation the upper 16 bits
would represent a 16-bit result, and the lower 16 bits would be
regarded as an underflow.
2. Duplicate sign bit elimination. Following a multiplication of two
16-bit values the nature of the representation results in two "sign
bits" in the result. For normal integer arithmetic this causes no
problem, but for fractional arithmetic a shift left by one is required
to normalize the result.
3. Saturation. If we perform an arithmetic operation that would cause
us to overflow, it can be useful to return the maximum (appropri-
ately signed) number that can be represented in the result register.
The alternatives which include firing an interrupt, saying the result
is undefined and is some other number, usually look less attractive
to DSP programmers.
These fractional operations can often be done at no extra cost to normal
integer operations on DSPs using special instructions or modes of
operation.
VisualDSP++ 3.5 C/C++ Compiler and Library Manual
for ADSP-219x DSPs
Compiler
1-107