Read Channel; Read/Reference Clock Multiplexer; Read/Write Head Select - HP 7957A Hardware Manual

Theory Of Operation
7957/7958
current thereby recording magnetic dipoles on the
disc.
The microprocessor-generated inner zone signal is
asserted when the positioner is within the inner
range of tracks (i.e., track numbers greater than
511). This signal selects the lower of two values of
write current. The lower value of write current is
selected because the recorded linear bit density on
the inner tracks is higher than on the outer tracks.
The lower value of write current improves
resolution.
3-20. READ CHANNEL
When the drive is selected and the interface Read
Gate signal is true, low-level read signals from the
selected data head are amplified. Since read data is
represented by the time position of the read sig-
nal's peak and since the peak is difficult to sense
directly, the read signal is differentiated to
produce a signal that changes state at the peak. As
a result, each peak corresponds to a "zero crossing."
Next, the differentiated signal is filtered to remove
high-frequency noise and minimize distortion. Then
the signal is digitized and applied to a pulse-former
circuit, which generates the Read Data signal. The
read data is decoded (from 2,7 RLL data to NRZ
data) and passed to the controller via balanced,
differential data lines NRZ Read Data± with its
associated read clocks transmitted via the
Read/Reference Clock±.
3-21. READ/REFERENCE CLOCK
MULTIPLEXER
When Read Gate is not asserted, Read/Reference
Clock signal is switched to Reference Clock, which
is Servo PLO divided by 2.
When Read Gate is asserted, the read data
separator PLO is synchronized to the preamble
data, and the Read/Reference Clock signal is
switched to the Read Clock.
3-22. READ/WRITE HEAD SELECT. The
Read/Write Head Select circuit controls up to
eight data heads. Functions included in the circuit
are:
• Head selection matrix
• Read/write switching logic
• Read preamplifier
• Write drivers
• Write Unsafe detection logic
The head address is determined by three interface
head Select lines (HS2
3
is not used in this disc
drive). The address is decoded by the Read/Write
Head Select circuit (refer to table 3-2).
Table 3-2. Head Selection
HS2
3
HS2
2
HS2
1
HS2
0
HP7957A
HP 7958A
0
0
0 0
0
0
0 0
0
1 1
1
0 0
1
0
2 2
0
0
1
1
3 3
0
1
0 0
4 4
0
1 0 1 - 5
0
1 1 0
-
6
0
1 1 1
- 7
3-10