HP 7957A Hardware Manual page 22

Interface Information
7957 A/7958A
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T
t _ _ _ _ _ _ ...
IJ
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F
Tl
DRIVE SELECT
DRIVE SELECTED
Tl
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2Sca NSEC
I£SDIAI5
Figure 2-1. Drive Selection/Deselect ion Timing
Table 2-4. Valid Head Select Values
HEAD SELECT LINES
2
3 22 21
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0
1 1
1 0 0
1 0 0
1
0
1
1 0 1
1 1 X
• READ GATE. The READ GATE timing is
shown in figure 2-4.
The following timing restrictions apply to the
READ GATE signal:
- When the drive performs a head switch opera-
tion, the controller should not activate READ
GATE until COMMAND COMPLETE is ac-
tivated, indicating completion of the head
switch.
- When performing a read following a write,
READ GATE should not be activated for at
least 500 nanoseconds after WRITE GATE is
deactivated.
2-6
HEAD SELECTED
2° HP 7957A HP 7958A
0
1
0
1
0
1
0
1
0
1
0
1
X
0 0
1 1
2 2
3 3
4 4
5 5
Inv
6
Inv 7
Inv Inv
Inv
Inv
Inv Inv
Inv Inv
Inv Inv
- READ GATE must be deactivated when
passing over a Write Splice. READ GATE must
be deactivated a minimum of 100 nanoseconds
(one bit time) before the Write Splice, and must
remain deactivated for a minimum of 100
nanoseconds following the Write Splice (see
figure 2-2).
- READ GATE must be activated at least 14
bytes before the Sync Pattern byte.
• DRIVE SELECTED. The drive activates this
signal within 250 nanoseconds after its drive
selection address is valid (see figure 2-1). This
signal is deactivated within 250 nanoseconds of
being deselected by the controller.