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Theory Of Operation
7957/7958
transfer request line RREQ. When the DMA Bus
Arbiter acknowledges the transfer by asserting
RACK, the DDC performs the following steps to
complete each I-byte transfer:
• Outputs buffer address onto DMA data bus.
• Generates NOMA WR strobe if data is being
transferred from the HP-IB Interface IC to the
buffers.
• Increments buffer address counter by 1 for next
transfer.
The DDC will continue this process until all of the
bytes specified have been transferred. The micro-
processor may set up the DDC to have both a
remote and local transfer operation active at the
same time. In this situation, the local and remote
DMA transfers are interleaved.
3-35.
ESDI PAL
The purpose of the ESDI PAL Circuit is to delay
the leading edges of READ GATE, WRITE GATE,
and ADDRESS MARK ENABLE going to the
HDA. Explanations for each case are given below.
In each case, an enable signal is generated which is
gated with the appropriate DDC signal. Two state
machines are implemented in the ESDI PAL. One
of the state machines is used to delay READ
GATE during the post-index ISG control, and the
other is used to generate the three enable signals
for READ GATE, WRITE GATE, and ADDRESS
MARK ENABLE (RGEN, WGEN, and AMEN
respectively).
The ESDI PAL powers up in an asserted low state.
The firmware does not change this state until the
READ/REFERENCE CLOCK from the HDA is
running. This is required for the state machines in
the ESDI PAL to reset. During a read or compare
header operation, the DOC asserts READ GATE
within a couple of READ CLOCK cycles after the
INDEX or SECTOR pulse. When a header is writ-
ten, or at the beginning of a format operation,
WRITE GATE has a similar delay from INDEX or
SECTOR. Thus, READ GATE could be asserted
over a write splice.
The ESDI PAL counter delays the leading edge of
READ GATE until the head is over the header
3-16
PLO sync field in order to a void this problem.
When the ESDI PAL detects an INDEX or
SECTOR pulse, counting is enabled by setting
(CNT) high. The ESDI PAL asserts RGEN high.
The microprocessor must set up this READ GATE
delay at power-on initialization. It does this by
writing a 7-bit value into the the counter. Once the
7-bit word has been set up, the microprocessor
strobes it into the counter by reading address
3000H. The value of the 7-bit word should be:
count
=
125 - (post-index ISG)
where the post-index ISG is in bits
This insures that READ GATE will be asserted 0.5
to 3.5 bits into the address PLO sync field.
The READ GATE delay circuitry also delays the
leading edge of READ GATE by 3-bit times
during a data field read. This is to compensate for
the delay of WRITE GATE during a data field
write. This insures that READ GATE is not as-
serted over the write splice.
3-36. WRITE GATE AND ADDRESS MARK
ENABLE
DELA Y
CIRCUIT.
The
ESDI
specification requires that WRITE CLOCK be ac-
tive for 2.5 cycles prior to the assertion of WRITE
GA TE, and that ADDRESS MARK ENABLE be
asserted a minimum of 100 ns after the assertion
of WRITE GATE. Since the DDC does not meet
these requirements by itself, additional hardware
was
added
to
delay
WRITE
CLOCK
and
ADDRESS MARK ENABLE by the required
amounts.
3-37.
ERROR CORRECTION
The DDC has the capability to perform 16-bit
CRC, or 48-bit ECC generation and checking on
the address and data fields. The DDC allows for
the microprocessor to program the desired ECC
polynomial, polynomial preset, and correction
span. An error correction cycle is performed in-
ternal to the DDC, however it must be initiated by
the microprocessor. When the correction cycle is
complete, the DDC contains information for the
microprocessor to compute the buffer address of
the first byte in the data field that contains the
error.
The microprocessor then completes the
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