HP 7957A Hardware Manual page 52

Theory Of Operation
7957/7958
Table 3-3. Mnemonic Table
Mnemonic Definition Source
ACSEN Address Chip Select Microprocessor Control,
Enable Clock Generation and
Stretcher
DCLK
o
CLOCK
Microprocessor Control,
Clock Generation and
Stretcher
DQCLK DQ Clock DMA PAL
EECLK*
EEPROM Clock Control Bit Register
EEDATA*
EEPROM Data
Status Bit
Register /Control Bit
Register
LREQ Local Request
DDC
NBUF2E Not Buffer 2 Enable DMA PAL
NDDRD Not Delay Read DMA Bus Arbiter Circuit
NDMARD Not DMA Read DDC/Control, Clock
Genera tion and Stretcher
circuit
NDMAWR Not DMA Write DOC/Control, Clock
Genera tion and Stretcher
circuit
*For disc drives with an EEPROM only.
3-20
Description
Used to enable ap-
propria te address and
chip select functions
during a microprocessor
transaction
Used to drive DMA Bus
Arbiter
Clock signal from DMA
PAL for remote
Used to clock informa-
tion into and from
EEPROM
Line use to transfer in-
formation in and out of
EEPROM
Activated by DOC to in-
itiate a local transfer
Activated by DMA PAL
to turn on Transceiver 2
for microprocessor
transactions
Used to generate delayed
NIOGO signal
This signal is activated to
provide a Read from the
DMA Buffers
This signal is activated to
provide a Write to the
DMA buffers