Signal Processing Latency - Lake LM 26 Operation Manual

Application Guide
When using automatic detection, the AES3 digital input is monitored and will switch the clock source back
and forth depending on the availability of an AES3 signal.
Please refer to the Lake Controller Operation Manual for additional information.
9.4.3 Dante Clock Configuration
Dante uses its own digital clocking technology across the Ethernet network to ensure that all Dante devices
are synchronized. As part of this logic, an order of priority is defined to identify which device becomes
the Dante Master. A Dante-capable device with a valid BNC Word Clock is chosen as the highest priority,
followed by a device with a valid AES3 signal, then SPDIF, then an internally generated clock.
Dante only operates at 48 kHz or 96 kHz, and therefore only uses the Primary Digital Clock to lock the
sample rate for the Dante Master. The Primary Clock on all Dante Slaves will be overridden by the Dante
Clock.
The front panel I/O Status View indicates if that device is selected as Dante Clock Master. Confirmation of
Dante Master / Slave status is also displayed in the Lake Controller.
For further information on Digital Clock configura-
tion and the Lake Controller user interface, please
refer to the Lake Controller Operation Manual.
9.4.4

Signal Processing Latency

The information in Table 9-1 lists the total latency for common input-output configurations.
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LM 26 Operation Manual rev 1.2.3
Input Configuration Output Configuration
Analog
48 kHz sync
96 kHz sync
48 kHz async
96 kHz async
44.1 kHz async
88.2 kHz sync
96 kHz sync 96 kHz sync
44.1 kHz async 44.1 kHz async
88.2 kHz async 88.2 kHz async
48 kHz async 48 kHz async
Table 9-1: Latency for Common Input-Output Configurations
Total Latency (ms)
Analog 1.036
Analog 1.207
Analog 0.951
Analog 1.215
Analog 1.182
Analog 1.214
Analog 1.181
0.872
1.363
1.345
1.356