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2.2 CPU Speed Selection
The clock synthesizer at location U47 makes it possible to change the frequency of
the microprocessor's system clock output without having to change the clock crys-
tal. Simply set the system clock divisor jumpers to adjust the frequency of the micro-
processor's system clock output. These system clock divisor jumpers are located at
J27–1/2 (IRQ3), J27–3/4 (IRQ2), J27–5/6 (IRQ1), and J27–7/8 (IRQ0). The jumper
configuration is set in IRQ3 through IRQ0. These four jumpers set the speed at
power-up as listed in Figure 2–2. The microprocessor frequency divided by the ratio
determines the system clock frequency.
2.3 Bcache Size Jumpers (CF1 and CF2)
The Bcache size jumpers are located at J27–11/12 (CF1) and J27–13/14 (CF2), as
shown in Figure 2–2. The AlphaPC 164LX is configured with 2MB of Bcache
during production; the other jumpers shown in Figure 2–2 (0, 1, and 4) are for other
implementations.
Note:
2.4 Password Bypass Jumper (CF3)
AlphaBIOS provides password protection. However, password bypass is provided
for system setup or startup when the AlphaBIOS password is unavailable.
Password bypass is enabled by inserting jumper CF3 in the J27 system configuration
jumper block. This disables the AlphaBIOS password verification and enables the
user to perform system setup and startup without the AlphaBIOS password. Pass-
word bypass also clears the password.
2.5 Boot Option Jumper (CF7)
The boot option jumper is located at J27–23/24 (CF7). The default position for this
jumper is out (Figure 2–2). This jumper selects the image to be loaded into memory
from the system flash ROM. With the jumper out, the AlphaBIOS firmware is
loaded. With the jumper in, the fail-safe booter is loaded. For more information
about the fail-safe booter, refer to the AlphaPC 164LX Motherboard Windows NT
User's Manual.
22 January 1998 – Subject To Change
The standard motherboard is manufactured with 128K
SSRAMs (21A04-C0 for Windows NT and 21A04-C1 for UNIX). An
OEM, however, can create a 4MB L3 cache variation using 256K
data SSRAMs.
CPU Speed Selection
System Configuration and Connectors
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