Pci Bus Overview - HP Compaq D315 Technical Reference Manual

Chapter 4 System Support
4.2

PCI BUS OVERVIEW

NOTE: This section describes the PCI bus in general and highlights bus
implementation in this particular system. For detailed information regarding PCI bus
operation, refer to the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the IGP and MCP or MCP-2 are organized as
multiple devices). A function is defined as the end source or target of the bus transaction. A
device may contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the chipset components and is not physically accessible. The AGP bus
that services the AGP slot is designated as PCI bus #1. All PCI slots reside on PCI bus #2.
Mem. Cntlr.
Function
HT Link I/F
Hyper Transfer Link Bus
HT Link I/F
PCI Bridge
Function
PCI
Bus #2
NOTE:
Not implemented in the D315 system.
Figure 4-1. PCI Bus Devices and Functions
Compaq D315 and hp d325 Personal Computers
4-2
Featuring the AMD Athlon XP Processor
IGP Component
Integrated
PCI
Graphics
Bus #0
Controller
MCP or MCP-2 Component
PCI Bus #0
Legacy SMBus
Controller
Function Function
PCI Connector 1
PCI Connector 2
PCI Connector 3
Second Edition – April 2003
PCI Bus #1
AGP
(AGP Bus)
Bridge
AGP Connector
Function
USB USB Network
Cntlr. A Cntlr. b Interface
Function Function Function
AC97 IDE
Audio Controller
Function Function