Nic Programming - HP Compaq D315 Technical Reference Manual

5.9.4 NIC PROGRAMMING

Programming the NIC consists of configuration, which occurs during POST, and control, which
occurs at runtime.
5.9.4.1 Configuration
The network interface function is a PCI device and configured though PCI configuration space
registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in
the following table:
Table 5–25. NIC Controller PCI Configuration Registers
NIC Controller PCI Configuration Registers (ICH Device 8/Function 0)
PCI
Conf.
Addr. Register
00-01h Vender ID
02-03h Device ID
04-05h PCI Command
06-07h PCI Status
08h Revision ID
09-0Bh Class Code
0Dh Latency Timer
0Eh Header Type
10-13h Cntrl. Reg. Base Addr. (Mem)
14-17h Cntrl. Reg. Base Addr. (I/O)
2C, 2Dh Subsystem Vender ID
NOTE:
Assume unmarked gaps are reserved and/or not used.
[1] ICH2 = 2449h
ICH4 = 103Ah
5.9.4.2 Control
The 82562 controller is controlled though registers that may be mapped in system memory space
or variable I/O space. The registers are listed in the following table:
Table 5–26. NIC Control Registers
Offset
Addr. / Register
00h SCB Status
02h SCB Command
04h SCB General Pointer
08h PORT
0Ch Flash Control Reg.
0Eh EEPROM Control Reg.
10h Mgmt. Data I/F Cntrl. Reg.
14h Rx Direct Mem. Access Byte Cnt.
18h Early Receive Interrupt
Not implemented in these systems (CardBus registers).
Table 5-25.
Value on PCI
Reset Conf.
Addr.
8086h 2E, 2Fh
[1] 34h
0000h 3Ch
0290h 3Dh
Xxh 3Eh
0002h 3E, 3Fh
00h DCh
00h DDh
8 DE, DFh
1 E0, E1h
0000h E3h
Table 5-26.
NIC Control Registers
No. of Offset
Bytes Addr. / Register
2 19h Flow Control Register
2 1Bh PMDR
4 1Ch General Control
4 1Dh General Status
2 1E-2Fh Reserved
2 30h Function Event Register
4 34h Function Event Mask Register
4 38h Function Present State Register
1 20h Force Event Register
Compaq D315 and hp d325 Personal Computers
Featuring the AMD Athlon XP Processor
Second Edition - April 2003
Technical Reference Guide
Register
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Min. Grant
Max. Latency
Capability ID
Next Item Pointer
Pwr. Mgmt. Functions
Pwr. Mgmt. Cntrl./Sts
Data
Value
on
Reset
0000h
DCh
00h
01h
08h
38h
01h
00h
FE21h
0000h
--
No. of
Bytes
2
1
1
1
10
4
4
4
4
5-35