HP Compaq D315 Technical Reference Manual page 48

Chapter 3 Processor/Memory Subsystem
The SPD address map is shown below.
Table 3–1. SPD Address Map (SDRAM DIMM)
Byte Description
0 No. of Bytes Written Into EEPROM
1 Total Bytes (#) In EEPROM
2 Memory Type
3 No. of Row Addresses On DIMM
4 No. of Column Addresses On DIMM
5 No. of Module Banks On DIMM
6, 7 Data Width of Module
8 Voltage Interface Standard of DIMM
9 Cycletime @ Max CAS Latency (CL)
10 Access From Clock
11 Config. Type (Parity, Nonparity, etc.)
12 Refresh Rate/Type
13 Width, Primary DRAM
14 Error Checking Data Width
15 Min. Clock Delay
16 Burst Lengths Supported
17 No. of Banks For Each Mem. Device
18 CAS Latencies Supported
19 CS# Latency
20 Write Latency
21 DIMM Attributes
22 Memory Device Attributes
23 Min. CLK Cycle Time at CL X-1
24 Max. Acc. Time From CLK @ CL X-1
NOTES:
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer's datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] Compaq usage. This system requires that the DIMM EEPROM have this
space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is
invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system
Tampering.
[11] Contains the socket # of the module (first module is "1"). Intended as backup identifier (refer to
note [10]).
Compaq D315 and hp d325 Personal Computers
3-6
Featuring the AMD Athlon XP Processor
Table 3-1.
SPD Address Map (SDRAM DIMM)
Notes Byte
[1] 25
[2] 26
27
[3] 28
29
30, 31
32..61
62
[4] 63
[4] 64-71
72
[4] [5] 73-90
91, 92
93, 94
[6] 95-98
99-125
[4] 126
[4] 127
[4] 128-131
[4] 132
133-145
146
[7] 147
[7]
Second Edition - April 2003
Description
Min. CLK Cycle @ CL X-2
Max. Acc. Frm CLK @ CL
X-2
Min. Row Prechge. Time
Min. Row Active to Delay
Min. RAS to CAS Delay
Reserved
Superset Data
SPD Revision
Checksum Bytes 0-62
JEP-106E ID Code
DIMM OEM Location
OEM's Part Number
OEM's Rev. Code
Manufacture Date
OEM's Assembly S/N
OEM Specific Data
Intel frequency check
Reserved
Compaq header "CPQ1"
Header checksum
Unit serial number
DIMM ID
Checksum
Reserved
Notes
[7]
[7]
[7]
[7]
[7]
[7]
[7]
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[9]
[9]
[9] [10]
[9] [11]
[9]
[9]