Main Memory Controller - HP Kayak XU800 Technical Reference Manual

AGP PCI Bus
Implementation
AGP 4x Bus
(133 MHz)
Universal
AGP
PRO
Connector
64-bit 66
MHz slots

Main Memory Controller

The main memory controller is integrated in the MCH supporting two
primary rambus channels (A and B).
DRAM Interface
The MCH provides optional Host bus error checking for data, address,
request and response signals. Only 300 MHz and 400 MHz Direct Rambus
devices are supported in any of 64, 128 or 256 Mb technology. 64 and 128
MBit RDRAMs use page sizes of 1 kbytes, while 256 Mb devices target
1 kbyte or 2 kbyte pages.
A maximum number of 64 Rambus devices (32 devices maximum per
channel) is supported. Both channels must be populated with paired
memory modules.
GX-Device 1
AGP Port
Interface
PCI-to-PCI
Hub Link 16-bit
Two PCI
PCI 64-bit 66 MHz
Hub (P64H)
PCI-to-PCI
2 System Board
Memory Controller Hub (8240)
Pentium III Processor
Device 0
I840
Memory
Controller Hub
(MCH)
PCI-to-PCI
I/O Controller
Hub (ICH)
Hub Link 8-bit
39