10 Gigabit Performance Traffic Patterns; Throughput Test; Latency Measurements - HP 5400zl Series Technical Overview

10 Gigabit performance traffic patterns

In the prior table, the performance levels for 10 Gigabit ports assume the underlying traffic patterns
reflect either one of the following minimum conditions to achieve wire-speed throughput.
• A single source traffic stream with an average packet size of 88 bytes or larger
• Two or more source traffic streams of any packet size down to the minimum value of 64 bytes
In the unlikely case where the average packet size is consistently smaller, the throughput will be less
than wire-speed. For example, consider a worst case scenario where the average packet size is 64
bytes. This would result in a throughput of approximately 70% to 80% of the rated wire-speed
capacity. HP ProCurve considers such minimum-sized, packet traffic scenarios being realized over an
extended period of time to be extremely atypical and unlikely to be experienced by customers in the
field.
Note that the limits described above do not apply to Gigabit ports.

Throughput test

A fully meshed performance test sends packets from each port to every other port during the test. This
type of test exercises both the modules and the backplane. These tests show the HP ProCurve Switch
5400zl, 3500yl, and 6200yl series to be wire-speed on all ports simultaneously.

Latency measurements

Latency is commonly measured as the amount of time it takes for a byte inside a packet to enter and
then leave the switch. Latency statistics are typically documented as including both the processing time
of the switch as it makes its forwarding decision and the time for the packet itself to enter and leave the
switch. In the prior tables, this definition of latency corresponds to the FIFO latency statistics. The
LIFO latency statistics that are also listed in the tables represent only the packet transmission time.
Almost all switches currently on the market are store and forward, so the entire packet is received into
the switch before the switch begins to transmit the packet out the egress port. Including the packet
receive time in the FIFO latency statistics is appropriate since this extra time is a contributing
component of the overall transit time of the packet as it moves through the network.
The latency figures for the HP ProCurve Switch 5400zl series are consistently low. Latencies this low
will not be a factor in general network operation, even with streaming video or VoIP applications. The
LIFO latency values are fairly consistent across all packet sizes because ingress and egress packet
processors operate on the header of the frame (not the whole frame), while the full frame is buffered in
and out of packet buffer memory. Memory transfers are scheduled to fit a full 1518-byte frame, so
frames are transferred in and out of memory in approximately the same amount of time regardless of
packet size. While the frame headers are being looked up and actions required for the frame on egress
are being coordinated among interface modules, the frame is transferred through the switching fabric
module.
The architecture used for ACL storage and processing is different among the HP ProCurve switches
listed in table 9. The HP ProCurve Switch 5400zl and 3500yl series have the additional performance
advantage gained through the use of the TCAM (see the appendix for more details). The HP ProCurve
Switch 5400zl and 3500yl series also have an additional performance advantage in the processing of
the routing table through the use of a "best match prefix" table (described previously in this section).
The HP ProCurve Switch 5400zl and 3500yl series support the use of PIM-SM and PIM-DM, but not
concurrently.
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