Pci Master Read Prefetch; Pci#2 Access #1 Retry; Pci Master 1 Ws Write; Pci Master 1 Ws Read - TMC TI5VG User Manual

Chapter 6 BIOS Configuration
CPU to PCI Write Buffer
When enabled, this option increase the efficiency of the PCI bus to and
speed up the execution in the processor. By default, this field is set to
Enabled.
PCI Dynamic Bursting
When enabled, this option combines several PCI cycles into one. By
default, this field is set to Disabled.
PCI Master 0 WS Write
When enabled, this option increases the write cycle speed. By default,
this field is set to Disabled.
PCI Delay Transaction
When enabled, this option delays PCI data transaction. By default, this
field is set to Disabled.

PCI Master Read Prefetch

When this item is enabled, the system is allowed to prefetch the next read
and initiate the next process. By default, this field is set to Disabled.

PCI#2 Access #1 Retry

This item enables PC#2 Access #1 attempts. By default, this field is set to
Disabled.

PCI Master 1 WS Write

When enabled, writes to the PCI bus are executed with 1 wait states. By
default, this field is set to Disabled.

PCI Master 1 WS Read

When enabled, reads to the PCI bus are executed with 1 wait states. By
default, this field is set to Disabled.

PCI IRQ Activated by

This field allows you to select the method by which the PCI bus
recognizes that an IRQ service is being requested by a device. The
default value is Level.
48 TI5VG Pentium VP3 ATX Motherboard User's Manual