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Chapter 6 BIOS Configuration
CPU to PCI Write Buffer
When enabled, this option increase the efficiency of the PCI bus to and
speed up the execution in the processor. By default, this field is set to
Enabled.
PCI Dynamic Bursting
When enabled, this option combines several PCI cycles into one. By
default, this field is set to Enabled.
PCI Master 0 WS Write
When enabled, this option increases the write cycle speed. By default,
this field is set to Disabled.
PCI Delay Transaction
When enabled, this option delays PCI data transaction. By default, this
field is set to Enabled.
PCI#2 Access #1 Retry
This item enables PC#2 Access #1 attempts. By default, this field is set
to Disabled.
AGP Master 1 WS Write
When enabled, writes to the AGP bus are executed with 1 wait states.
By default, this field is set to Enabled.
AGP Master 1 WS Read
When enabled, reads to the AGP bus are executed with 1 wait states.
By default, this field is set to Enabled.
PCI IRQ Activated by
This field allows you to select the method by which the PCI bus
recognizes that an IRQ service is being requested by a device. The
default value is Level.
Assign IRQ for USB/VGA
These fields allow you to enable or disable the IRQ for USB and VGA.
By default, these fields are enabled.
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MI7VGA User's Manual
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