Sharp MZ-5500 Tehnical Manual page 75

C:J
D
--I
-f3 --F33B
I I I I [±]I-H+I
Fig. 11-
5
(B) Same keys are inaperative:
Cheeking key eontaets
Conneet the keyboard to the System Unit, and turn on the
system with the CTRL and ALG (a, c) keys depressed and
held . After making sure all the indicators. come on, press
the keys in the order shown by the arrows in the above
figure. If no defective key contact exists, all the indicators
will go off . If any defective contact exists, alt the indicators
will remain on. If a wrong key is pressed and the indicators
eome on, they will 90 off when the eorrect key is sub ­
sequently pressed .
If no eontact trouble exists when alt the keys have been
operated , the CAPS indicator will come on, indicating that
the key cheek was normal.
11-3 Key search timing
Slngll klY op.'lIlon
I
eNlllr ing
.'\..W t~ 1 I fIoL
II" f " _ _ _
- - - I
Boun..
~
(11 11 !JA I A _ _ _ _ __
---4nL-_~;~1-_2_by_I
.. _ d._II____
___lL
Fig.11-
b
To prevent ehattering and bounce, the same key data is
cheeked twice during each search, and only matching 'key
data is regarded as correct. While the search cycle is 5.5ms,
it is ex tended to 16.5ms if a bounce
occurs' ~
t\"YI~ ~~-------
~~Y2
~ fwutH.
IlAlAI
_ _ __ ___
_ _ ----'
lJl:'l
I ~A
JA _ _ __ _ _
fLJl~f.L_
. . . . . . .
: ~~1
----::=--::-:c;-:-----­
K~Y2 IJATA
Fig . 11-?
Key search sequence for two-key operation is
th~
same as
that for single key operation. When two keys are simul­
taneously pressed, key data for the first and second keys
are successively transferred.
11-4
Eight-bit keyboard processor
J..IPD80C49
Highlights
1) Single-chip, 8-bit microprocessor.
2) 6uilt-in 2K x 8 bit ROM.
3) On ·chip 128K x 8 bit RAM.
4) Interruption service capability.
5) 1/0 port: 8 bits x 2
Oata bus (serving also as 1/0 port): 8 bits x 1
6) Built·in clock generator.
7) Single +2 .5 to +6V power supply.
Pin configuration
TO Vcc
XTALI
Tl
XTAU
1'27
RESET
1'26
SS
1'25
JNT
1'24
EA Pl7
RD
PI6
PSEN
1'15
WR
1'14
ALE
PI3
DHO
p
12
DDl
1'11
OH2 1'10
OD3 Voo
084
PROG
DH5
1'23
086
P22
DH7
1'21
Vss
20
21
1'20
Fig.l1-ß
Pin functions
Pl0 -P17:
1/0 port (port 1 )
P20 ·P27:
1/0 port (port 2)
OBO·067: Oata bus
TO, Tl: Test
TFJT:
Interrupt
RO:
Read
WR: Write
ALE . Address latch enable
PSEN:
Program store enable
RESET: Reset
SS: Single step
EA: External access
XTAL1,2: Ouartz inputs
VOO: Standby eon trol
t<