Sharp MZ-5500 Tehnical Manual page 26

I/U bit
map
(1) System
board
Table 2 - 2c\.
OEV,ICE AOD
8255
DlOH
[G' O UP A .
Mode 1
Group B
Mode 0
Dl1H
012H
(013H)
NOTES :
MZ-5500/5600
BIT SIGNAL NAME
fAD OATAl
PAl
OATA~
PA2 OATA3
PA3
DATA4
PA4
nATAS""
PA5
6DATA6
PA6
DATA7
PA7
DATA8
PBO
BUSY
PBl PE
PB2
POTA
PB3 DK
PB4 SRK
PB5 CO
PB6
er
PB7 MOTOA ON
PCD
OC
PCl STC
PC2
EXCLK EN
PC3 IA-PAT
PC4
PC5 STRÖBE
PC6 ACK
PC7
1/0
OUT
Data output to Centronics I/F (negative polarityl.
Null codes are hex F F.
Centronics I/F busy (busy it zero ,)
Centronics I/F.
Centronics I/F select signal (selecu it one.)
Oata bit from keyboard
} K,y
IN
Output requested trom keyboard
Carrier sense }
Called signal
fCir
synchrOnQI~
mode
MFD motor on $latus input
OUT
Data bit to keYboard}
OUT Strobe to keyboard
OUT
BSC external dock (BSC if High)
OUT Interrupt bV ACK input to Centronics I/F.
OUT Centronia I/F STROBE output (LI)
IN Centronia I/F ACK 'input
OUT Not used .
AFTER
P/O
Input
mode
(FF 'H)
Mode
input
Input
mode
(FFH)
INITIAL
OEFAULT
Output
mode
(FFH)
Mode
input
1
0
0
0
0
1
X
X
1) Group ,A is used in Mode 1.
2) Group B is used in M'ode O.
3) The desired bit otfthe output to Group C may be set or reset using the control register (013HI.
4) The bit PC6 is an interrupt enable tlag (INTEl. and is set or reset by the CPU.
5) While 'the AC!< may be read by PC3, is needs not be read
8S
its Status is known to the CPU via the PIC.
Table Z-2~
OEVICE AOO
BIT SIGNAL NAME
1/0
AFTER
P/O
AY·3·8912 230H
(Sound IC)
OUT
Input
IOA4 MOTOA ON
Drive motor on signal (on if Low ,)
mode
IOA5 MAO
} Am IAOOOOH-BFFFFHI b,nk
,,'eet
';gn,'
(FFH)
IOA6 MAl
IOA7 MA2
PORT·A 060H 100 High Den
( LS5411
101 ASTSW
RESET switch input (on if zero) - MFO selection
,
102
DIP SWl SWl
103
DIP SW2
SW2
Input
IN
System DIP switches
mode
104
DIP
sm
SW3
(see next page)
105
DIP SW4 SW4
106 DIP SW5
SW5
107 DIP SW6
SW6
INITIAL
DEFAULT
0
0
0
0
t
0
0
Input
mode
23