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ii)
mi1
(Non-Maskable Interrupt)
With the MZ-5500/5600 series, NMl to the 8086 CPU is used for the following
two purposes:
(1) System reset
The 8086 does not have the function to send the dynamic
RAM
refresh
signal as with the
Z-
80.
Whereas, DREQ i5 issued in the prescribed
period from the CTe
to DMA read
·
the dynamic
RAM
to refresh it.
If the system is reset hardware
-
wise, refresh is suspended for a certain
period which may possibly destruct the memory contents.
Therefore, tbe
system will be re
-
initialized with NMI by the software, instead of reset.
(2) Timeout monitor
Since the MZ
-
5500/5600 is normally a non-ready system, accessing the
memory or 1/0 area from which no ready signal is retllrned due to
a
software bug, it makes the epu stoppeu in appearance
.
So, the timeout
monitor circuit is provided by which the ready sjgnal is forced to return
unless the ready signal was not returned within the predetermined tjme
and NMl is issued to the epu at the same
time
to inform a timeout error.
3-2. Handling of user interrupt
i) Hardware
As there are several interrupt signals used for the MZ-5500/5600 expansion
slots, only the
IR-
26 is open for user's use.
The user must pay attentior.
to the following conditions when designing the
int~rrupt
circuit.
°
Since the 8259A applies the inte
r
rupt to the CPU upon detection
oE
Ili
g
h
state of interrupt request, the interrupt request signal has to
be
retained until the epu acknowledges it.
Ther
e
fore, it is
ne
cessary t
o
use the device that can clear the interrupt request by a softwar
e
commnnd
or the hardware that may clear it via the
1/0
port.
t5v
Open collector
Opec coll ec tor
IR- 2b
------o(J---!
Q
I~ltff
lR-26
-o(]---i
A'ioW(
1/0 decode
:;>u
IL
(ex;
1BOH)
-U
lssue th
Force th
e
port l ow l
e
vel at
at
t
h e l
NT
res e
t
"
e beginn"
command
.
th
e
beginning
oE
the interrupt
lnterrupt
lng
o
f the
processi ng routin
e.
processing r
o
utine.
2?
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