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-
-
5-1
.
Expansion signal description (common for the
MZ-
5S00 and
MZ-
S600)
In/Out
Signal
name
Out
AO
-
AI9
DO-
DIS
MRDC
MWTC
,
AMWC
ln/Out
Out
Out
IORC
10WC, AIOWC
Out
Out
JNTA
IOACC
Out
Out
MAO-MA2
Out
Function
°Memory, 1/0 address signal which represents:
IOACC=l: Memory addr
e
ss
10ACC=O
:
1/0 address
°AO functions the same as BHE for low order byte
(DO
-
D7 ) of the data bus.
°Pay attention to it that an invalid address may be
issued
a
t a time when addre
ss
ing signal
cha
ng
es
.
°A 16-bit data signal which is used for transfer
between th
e
CPU and the memory or the
1/0,
or, data
transfer b
e
tween th
e
memory and the 1/0 during DMA.
°Memory read
s
ignal.
°Me~ory
writ
e
signal
.
°Ihe MWIC
s
ignal i
s s
h orter by one CPU clock than the
AMWC signal, and the write da ta is e
s
tablished at a
high to low transition of the signal.
°During DH!,-, the
s
e two signals are issued at the same
timing.
°r/o r
e
ad signal
.
°1/0 write signal.
°Ihe
IOWC
signal is shorter by one CPU clock than the
AIOWC signal, and the write da ta is es tab lishe.d at a
high to low tl-ansition of the
s
ignalt
°During DMA, these two signals are issued at th
e s
ame
timing
.
°lnterrupt acknowledge signal from the CPU.
°Ihe signal used to indicate that the
epu
is accessing
the 1/0.
Ihe memory decoder must be enabled with
lOACC~1
and the 1/0 decod
e
r must be enabled with
lOACC=O.
°Bank select signal for the memory address,
AOOOOH-
BFFFFH.
Each bank is used in the following
manner:
MAO HAI HA2
1
1
1
0
I
I
1
0
1
0
0
1
1
1
0
0
1
0
1
0
0
0
0
0
Reserved
Not used
Not
us
ed
Not u
s
ed
Not used
Not used
Not used
Not used
°Ready signal returned from the device which is mapped
on
th
e
XACK area of
~he
memory map and 1/0 map.
°Must be driven by the open collector to perform
wired
-
OR.
XACK
In
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