Sharp MZ-5500 Tehnical Manual page 74

lable
11- 1
Dir;.ection
Signal name
CPU to keyboard Keyboard to CPU
DC
Send data 'READY' signal
STC Strobe
Request to Send (strobe
ror key data)
DK READY and ACK signals Send data
SRK None
Aequest to Aeceive (CPU)
(2) Key data transfer procedure
1) From keyboard to CPU
liC
u
0
src
Execution
0'
~
I
key
process
mr
I
d61 d5fdOl
p.nl
L
ntr
~
W",it
u
Fig. 11-
.:3
Ta disable both the keyboard and the CPU interrupt,
set both
oe
and
DR
to zero.
Keyboard: When key search, code translation, and
other necessary entry data processing is
completed, the keyboard starts transferring
entry data to the CPU. First. it waits until
OC is set to one. The waiting time is
normally 3ms; for direct keys, it is 1ms .
If
a time-out occurred, the keyboard exits the
data send seQuence. When OC is set to one,
the keyboard sets SR K to zero to interrupt
the CPU.
CPU: After acknowledging the interrupt, the
CPU verifies that
DR
is zero . If
DK
is one,
the CPU identifies the transferred data as
noise, and exits the interrupt service
routine. It then sets STC to zero.
Keyboard: When STC is set to one, the ' keyboard
waits until STC is set to zero. The maxi ­
mum waiting time is 500ms.
Ir
a time-out
occurred, keyboard control returns to the
initialization routine. When verifying STC=
0, the keyboard send data Eß and SR K to
one.
CPU: Receiving the Eß, the CPU sets STe to 1 to
reQuest the keyboard for the next data
send.
Keyboard: Seeing STC is set to one, the keyboard
waits for STC to be set to zero.
(
CPU: Sets STC to zero to read data from the
keyboard, then sets STe again to one to
re Quest the keyboard for the next data
send .
Keyboard: When STC is set to one, the keyboard sets
P.ß. and waits for STC to be reset to zero.
When STC is set again to one, it sets OK to
zero.
CPU:
Sets STe to zero to read P.8. then sets STC
to one to set the result of the parity <;heck
into OC. If a parity error occurred, OC
is zero; if no parity error occurred,
UC
is 1.
The CPU sets STC to one to complete the
transfer seQuence.
Keyboard: When STC is set to zero , the keyboard
reads the result of the parity check. When
STC is set to one, it sets
OK
to one to
enable an interrupt from the CPU, and
completes the data transfer sequence . 1f a
parity error was detected , the keyboard
terminates the data transfer sequence, then
tries the same data send again .
Repeat nine times.
2) Form CPU to keyboard
m:
. I.
d.c da
1
d2
1
d'
1
dO
1" ·1\ 1
SlfK
Fig. 11-
q.
CPU: Waits for up to 100ms for
0
K to be set to
one. If OK is still zero 100ms later, the CPU
identifies it as a keyboard error and exits
the seQuence. After verifying that OK is
one, the CPU sets
oe
and STC to zero, to
interrupt the keyboard .
Keyboard: When the keyboard is interrupted by the
CPU, it enters the data receive sequence
and verifies DC=O. If OC is one, the key·
board identifies STC=O as noise, and exits
the interrupt sequence. If OC is zero, it sets
OK to zero.
CPU:
Verifies that OK is zero 70115 after inter
·
rupting the keyboard. The CPU then sets
STC to one to set d4, then re sets STC to
zero again.
Keyboard: Seeing STC is set to one, the keyboard
reads data when STC is reset to zero . .
(
CPU: Sets STC to one to set data, then resets
STC to zero.
Keyboard: Reads P.ß. to check parity, then sets the
result of this parity check when STC is set
to 1. If no parity error occurred, it sets
DK
to one; if a parity error occurred, OK is
zero. The keyboard sets OK to zero when
STC is reset to zero .
CPU: Sets STC to one to read the resul t of the
parity check. It then temporarily sets
STC
to zero and then sets it again to one,
to terminate operations.
.. Repeat five times.
(3) Keyboard check method
(A)
If
the keyboard is locked up:
Checking the keyboard processor
Connect the keyboard to the System Unit, then turn on th e
system without operating any keys . If only the CAPS
indicator comes on, ROM check for the keyboard processor
(B0C49) is norm at If all the indicators come on, it indicatp.s
, a ROM
~heck
error occurred. Probably
t~e
keyboard
processor (BOC49) is malfunctioning .
'71