Sony HCD-FLX7D Service Manual page 110

HCD-FLX5D/FLX7D
Pin No. Pin Name
OE0
43
44 CS0
45 WE0
VDDE
46
WMD1
47
VSS
48
49 WMD0
PAGE2
50
VSS
51
PAGE1, PAGE0
52, 53
54 BOOT
BTACT
55
BST
56
MOD1
57
58 MOD0
EXLOCK
59
VDDI
60
VSS
61
62, 63 A17, A16
A15 to A13
64 to 66
67 GP10
DECODE
68
AUDIO
69
70 VDDI
VSS
71
D15 to D12
72 to 75
VDDE
76
77 to 80 D11 to D8
VSS
81
A9, A12 to A10
82 to 85
TDO
86
TMS
87
XTRST
88
89 TCK
TDI
90
VSS
91
A8 to A3
92 to 97
98, 99 D7, D6
VDDI
100
VSS
101
102 to 105 D5 to D2
106 VDDE
D1, D0
107, 108
A2, A1
109, 110
VSS
111
110
I/O
O
Output enable signal output to the S-RAM
O
Chip select signal output to the S-RAM
O Write enable signal output to the S-RAM
—
Power supply terminal (+3.3V)
I
S-RAM wait mode setting terminal Fixed at "H" in this set
—
Ground terminal
I S-RAM wait mode setting terminal Fixed at "L" in this set
O
Page selection signal output terminal Not used
—
Ground terminal
O
Page selection signal output terminal Not used
I Boot mode control signal input terminal Not used
O
Boot mode state display signal output terminal Not used
I
Boot trap signal input from the digital audio interface receiver
I
PLL input frequency select terminal
I Mode setting terminal
I
PLL lock error and data error flag input from the digital audio interface receiver
—
Power supply terminal (+3.3V)
—
Ground terminal
O Address signal output terminal Not used
O
Address signal output to the S-RAM
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter
O
Not used
O
Decode signal output to the system controller
I
Bit 1 input terminal of channel status from the digital audio interface receiver
— Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
—
Power supply terminal (+3.3V)
I/O Two-way data bus with the S-RAM
—
Ground terminal
O
Address signal output to the S-RAM
O
Simple emulation data output terminal Not used
I
Simple emulation data input start/end detection signal input terminal Not used
I
Simple emulation asychronous break input terminal Not used
I Simple emulation clock signal input terminal Not used
I
Simple emulation data input terminal Not used
—
Ground terminal
O
Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
—
Power supply terminal (+3.3V)
—
Ground terminal
I/O
Two-way data bus with the S-RAM
— Power supply terminal (+3.3V)
I/O
Two-way data bus with the S-RAM
O
Address signal output to the S-RAM
—
Ground terminal
Description
"L": 384fs, "H": 256fs (fixed at "H" in this set)
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)