Siemens ERTEC EB 200 Manual page 7

List of Figures
Figure 1: Block Diagram of the EB 200......................................................................................................................... 10
Figure 2: ERTEC 200 Block Diagram ........................................................................................................................... 11
Figure 3: Reset Logic of the EB 200 ............................................................................................................................. 20
Figure 4: Overview of Clock System of the EB 200 ...................................................................................................... 21
Figure 5: Connector Positions on the EB 200 ............................................................................................................... 29
Figure 6: Front Element of the EB 200 ......................................................................................................................... 42
List of Tables
Table 1: Selection of Operating Modes and System Functions for EB 200 .................................................................. 13
Table 2: Boot Mode Selection for EB 200..................................................................................................................... 13
Table 3: IRQ Interrupts ................................................................................................................................................. 14
Table 4: FIQ Interrupts.................................................................................................................................................. 15
Table 5: CS Areas of the EB 200.................................................................................................................................. 15
Table 6: GPIO [31:0] on EB 200 ................................................................................................................................... 17
Table 7: GPIO [44:32] on EB 200 as Alternative Function............................................................................................ 18
Table 8: Overview of AHB Master-Slave Access .......................................................................................................... 23
Table 9: Function Groups with Memory Segments Used.............................................................................................. 23
Table 10: Detailed Memory Segment Distribution in the EB 200 .................................................................................. 25
Table 11: Default Settings of EMIF Registers on the EB 200 ....................................................................................... 28
Table 12: Pin Assignment for PCI Interface.................................................................................................................. 31
Table 13: Pin Assignment for LBU Interface................................................................................................................. 33
Table 14: Pin Assignment for External DC Supply ....................................................................................................... 33
Table 15: Pin Assignment for Ethernet Switch Interface (Downlink) ............................................................................. 34
Table 16: Pin Assignment for UART ............................................................................................................................. 34
Table 17: Pin Assignment for GPIO [15 to 0]................................................................................................................ 35
Table 18: Pin Assignment for GPIO [31 to .16]............................................................................................................. 35
Table 19: Pin Assignment for GPIO [44 to 32].............................................................................................................. 36
Table 20: Pin Assignment for X30 EMIF Address Bits.................................................................................................. 36
Table 21: Pin Assignment for X31 EMIF Data Bits ....................................................................................................... 37
Table 22: Pin Assignment for Connectors of I/O Adapter ............................................................................................. 37
Table 23: Pin Assignment for Trace Interface............................................................................................................... 38
Table 24: Pin Assignment of JTAG Interface................................................................................................................ 39
Table 25: Pin Assignment for Byte Blaster FPGA Programming Interface ................................................................... 39
Table 26: Pin Assignment for CPLD Programming Interface........................................................................................ 40
Table 27: Connector X10 for Boot Settings and Some Configuration Settings ............................................................. 41
Table 28: Connector X11 for Configuration and System Settings................................................................................. 41
Table 29: Function of LEDs on Front Panel of the EB 200 ........................................................................................... 43
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
7
EB 200 Manual
Version 1.1.4