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2.4.1
Reset Button
The EB 200 has a reset button that initiates a manual reset of the EB 200 without disconnecting the voltage supply.
2.4.2
PCI Reset
During PCI mode, the host reset controls the evaluation board directly.
2.4.3
Watchdog and Software Reset
Additional reset events can be initiated by the watchdog or a software reset. Both reset events have the same effect
as a debug reset.
2.5
Clock System of the EB 200
2.5.1
Clock-Pulse Supply of PCI Interface
The PCI bus supplies the PCI interface of the EB 200 with 33 MHz.
2.5.2
Clock Pulse Supply of EB 200 via a Quartz Crystal
By default, a 25 MHz quartz crystal supplies the EB 200 via the ERTEC 200 pins CLKP_A and CLKP_B.
2.5.3
Clock Pulse Supply of EB 200 via an Oscillator
Optionally, the EB 200 can also be supplied with an oscillator clock pulse. In this case, the 25 MHz clock pulse is feed
at the ERTEC 200 pin CLKP_A.
In both cases, the available 25 MHz clock pulse generated in the ERTEC 200 via the clock pulse output REF_CLK
can be used by external PHYs. The following clock pulses are generated by an internal PLL.
Operational clock for ARM946E-S, 50/100/150 MHz
Clock pulse for isochronous control, 100 MHz
Clock pulse for SDRAM interface, 50 MHz
Figure 4: Overview of Clock System of the EB 200
2.5.4
Cycle for F-Timer
On the EB 200, a separate 1 MHz clock pulse is generated for the F-timer via a CPLD.
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
21
EB 200 Manual
Version 1.1.4
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