External Memory Interface (Emif); Table 4: Fiq Interrupts; Table 5: Cs Areas Of The Eb 200 - Siemens ERTEC EB 200 Manual

FIQ # BLOCK
SOURCE
0 Watchdog
1 APB_Bus
2 Multilayer_AHB
3 PLL Stat
Register in
SCRB
4 ARM processor
5 ARM processor
6 Optional
7 Optional

Table 4: FIQ Interrupts

2.1.8

External Memory Interface (EMIF)

SDRAMs, SRAMs, and any I/O blocks can be connected to the external memory interface. In total, 5 chip-select lines
are available:

1 CS line for SDRAM with 16/32-bit data width

4 CS lines for asynchronous memory and I/O with 8/16/32-bit data width and assignable timing
The EB 200 has a socketed boot Flash to enable a simple firmware update in stand-alone mode. The boot medium is
always expected on chip select signal CS_PER0_N. The socketed boot Flash is addressed with CS_PER0_N by
means of boot jumper J2 = "External ROM 8-bit data width" (see Section 8). The 4-Mbyte firmware Flash is then
selected with CS_PER1_N. If the EB 200 is operated with a debugger (ICE), the boot Flash can be omitted as the
firmware Flash can be programmed directly. The following blocks of the EB 200 can be selected with the chip-select
lines:
Chip Select I/O
CS_PER0_N Boot Flash / FLASH
CS_PER1_N FLASH
CS_PER2_N CPLD, Ethernet, external
I/O
CS_PER3_N FPGA for accesses to the
PC host system
CS_SDRAM_N SDRAM

Table 5: CS Areas of the EB 200

The size of the chip select areas of CS_PER0_N - CS_PER3_N is defined as 16 Mbytes. The memory areas indicated
above appear mirrored correspondingly often.
The SDRAM can be regarded functionally as a dual-port RAM because the LBU interface, IRT switch, and
ARM946E_S all have access to the memory due to the multimaster capability of the ERTEC 200.
Copyright © Siemens AG 2010. All rights reserved.
Technical data subject to change
SIGNAL DEFAULT
Rising edge
Rising edge
Rising edge
Rising edge
COMMRX Rising edge
COMMTX Rising edge
Optional Rising edge
IRQ[15:0]
Optional Rising edge
IRQ[15:0]
Flash-Boot 8 Bit
512 Kbytes (8-bit)
fixed wait states
/ SRAM 4 Mbytes (16-bit)
fixed wait states
15
COMMENT
Watchdog 0 – timer has expired
Access to non-existing address on the APB
Access to non-existing address on the
AHB
Group interrupt of:
-
I/O QVZ (EMIF: memory controller)
- PLL loss state
- PLL lock state
See system control register
PLL_STAT_REG
Interrupt for comm channel (receive)
Interrupt for comm channel (transmit)
User-programmable IRQ source
User-programmable IRQ source
Function
Flash-Boot 16 Bit
4 Mbytes (16-bit)
8 Mbytes (32-bit)
16 Mbytes (32-bit) fixed wait states
16 Mbytes (32-bit) ready timing
64 Mbytes
fixed wait states
fixed wait states
EB 200 Manual
Version 1.1.4