Circuit Description; Receiver Circuits - Icom IC-F3 Service Manual

SECTION 4

4-1 RECEIVER CIRCUITS

4-1-1 ANTENNA SWITCHING CIRCUIT
Received signals are passed through the low-pass filter
(L1–L3, C1–C7 for IC-F3/S, L1–L3, C3, C5, C7 for IC-F4/S).
The filtered signals are applied to the ⁄
switching circuit (D8 for IC-F3/S D406, D8 for IC-F4/S).
The antenna switching circuit functions as a low-pass filter
while receiving. However, its impedance becomes very high
while D8 (IC-F3/S)/D406 and D8 (IC-F4/S) is/are turned ON.
Thus transmit signals are blocked from entering the receiv-
er circuits. The antenna switching circuit employs a ⁄
diode switching system. The passed signals are then
applied to the RF amplifier circuit.
4-1-2 RF CIRCUIT
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit are amplified
at the RF amplifier (Q12) after passing through the tuneable
bandpass filter (D9, D10, C83 for IC-F3/S, D10, L413, C79
for IC-F4/S). The amplified signals are applied to the 1st
mixer circuit (Q13) after out-of-band signals are suppressed
at the tuneable bandpass filter (D11, D12, D21, D22, C94 for
IC-F3/S, D11, D12, D401, C94 for IC-F4/S).
Varactor diodes are employed at the bandpass filters that
track the filters and are controlled by the CPU (IC8) via the
expander IC (IC10) using T1–T4 signals. These diodes tune
the centre frequency of an RF passband for wide bandwidth
receiving and good image response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
The 1st mixer circuit converts the received signal to a fixed
frequency of the 1st IF signal with a PLL output frequency.
By changing the PLL frequency, only the desired frequency
will be passed through a crystal filter at the next stage of the
1st mixer.
• 2nd IF AND DEMODULATOR CIRCUITS
Squelch level
adjustment pot
AF signal "DET"

CIRCUIT DESCRIPTION

type antenna
4
4
8
R92
Active
filter
FM
detector
9 10
The signals from the RF circuit are mixed at the 1st mixer
(Q13) with a 1st LO signal coming from the VCO circuit to
produce a 31.05 MHz (IC-F3/S) or 46.35 MHz (IC-F4/S) 1st
IF signal.
The 1st IF signal is applied to a pair of crystal filters (FI1) to
suppress out-of-band signals. The filtered 1st IF signal is
applied to the IF amplifier (Q14 for IC-F3/S, Q400 for IC-
F4/S), then applied to the 2nd mixer circuit (IC2, pin 16).
type
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
The 2nd mixer circuit converts the 1st IF signal to a 2nd IF
signal. A double conversion superheterodyne system (which
converts receive signals twice) improves the image rejection
ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier is applied to the 2nd
mixer section of the FM IF IC (IC2, pin 16), and is mixed with
the 2nd LO signal to be converted to a 450 kHz 2nd IF sig-
nal.
The FM IF IC contains the 2nd mixer, limiter amplifier, quad-
rature detector and active filter circuits. A 2nd LO signal
(30.6 MHz for IC-F3/S, 45.9 MHz for IC-F4/S) is produced at
the PLL circuit by dividing it's reference frequency.
The 2nd IF signal from the 2nd mixer (IC2, pin 3) passes
through a ceramic filter (FI2) to remove unwanted hetero-
dyned frequencies. It is then amplified at the limiter amplifi-
er (IC2, pin 5) and applied to the quadrature detector (IC2,
pins 10, 11) to demodulate the 2nd IF signal into AF signals.
4-1-5 AF CIRCUIT
AF signals from the FM IF IC (IC2 pin 9) are applied to the
mute switch (IC4, pin 1) via the AF filter circuit (IC3b, pins 6,
7). The output signals from pin 11 are applied to the AF
power amplifier (IC5, pin 4) after being passed through the
[VOL] control (VR board, R1).
2nd IF filter
450 kHz
FI2
7 5 3
Noise Noise
comp.
detector
Mixer
Limiter
amp.
RSSI
11 12 13
"NOIS" signal to the CPU pin 19
"SD" signal to the CPU pin 98
R5
X3
4 - 1
PLL IC
IC1
17 16
2 or 3
2
X1
15.3 MHz
IC2 TA31136F
16
1st IF from the IF amp.