Timer/Counter Operation; Introduction; Pacer Trigger Source - NuDAQ PCI- 9113A User Manual

5.3

Timer/Counter Operation

The PCI-9113A has an interval timer/counter 8254 on board. Refer to
section 3.5 for the signal connection and the configuration of the
counters.
5.3.1

Introduction

One 8254 programmable timer/counter chip is installed in PCI-9113A.
There are three counters in one 8254 chip and 6 possible operation
modes for each counter. The block diagram of the timer/counter system
is shown in following diagram .
2 MHz Clock
Figure 5.3.1 Timer/Counter System of PCI-9113A.
5.3.2

Pacer Trigger Source

The timer #1 and timer #2 are cascaded together to generate the timer
pacer trigger of A/D conversion. The frequency of the pacer trigger is
software controllable. The maximum pacer signal rate is 2MHz/4=500K
which excess the maximum A/D conversion rate of the PCI-9113A
(100KHz). The minimum signal rate is 2MHz/65535/ 65535, which is a
very slow frequency that user may never use it. The output of the
programmable timer can be used as the pacer interrupt source or the
timer pacer trigger source of A/D conversion. In software library, the timer
#1 and #2 are always set as mode 2 (rate generator) or mode 3.
8254 Chip
CLK0
C
Counter #0
G0
G
C
Timer #1
'H'
G
C
Timer #2
'H'
G
OUT0
O
Timer Pacer
O
O
Operation Theorem 35