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4.8
Software Trigger Register
To generate a trigger pulse to the PCI-9113A for A/D conversion, you just
write any data to this register, then the A/D converter will be triggered.
Address: BASE + 8
Attribute: write only
Data Format:
Bit
BASE+8
4.9
Interrupt Control and Readback Register
The PCI-9113A has a dual interrupt system, thus two interrupt sources
can be generated and be checked by the software. This register is used
to select the interrupt sources.
Address: BASE + 6
Attribute: write and read
Data Format:
Bit
BASE+12
ISC0: IRQ0 signal select
0: IRQ on the ending of the AD conversion (EOC)
1: IRQ when FIFO is half full
ISC1: IRQ1 signal select (Timer Interrupt only)
FFEN: FIFO enable pin
0: FIFO Enable (Power On Default value)
1: FIFO Disable
(To reset FIFO, set FFEN sequence as 0 -> 1 -> 0)
4.10 Hardware Interrupt Clear Register
Because the PCI interrupt signal is level trigger, the interrupt clear
register must be written to clear the flag after processing the interrupt
7
6
5
X
X
X
7
6
5
X
X
X
4
3
X
X
4
3
2
X
X
FFEN
Registers Format
2
1
0
X
X
X
1
0
ISC1
ISC0
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