A/D Trigger Source Control; A/D Data Transfer Modes - NuDAQ PCI- 9113A User Manual

5.1.3

A/D Trigger Source Control

The A/D conversion is started by a trigger source, and then the A/D
converter will start to convert the signal to a digital value. In PCI-9113A,
two internal sources can be selected: the software trigger or the timer
pacer trigger. The A/D operation mode is controlled by A/D trigger mode
register. Total two trigger sources are provided in the PCI-9113A. The
different trigger conditions are specified as follows:
Software trigger (TSSEL=0)
The trigger source is software controllable in this mode. That is, the A/D
conversion is starting when any value is written into the software trigger
register. This trigger mode is suitable for low speed A/D conversion.
Under this mode, the timing of the A/D conversion is fully controlled by
software. However, it is difficult to control the fixed A/D conversion rate
unless another timer interrupt service routine is used to generate a fixed
rate trigger. Refer to interrupt control section (section 5.2) for fixed rate
timer interrupt operation.
Timer Pacer Trigger (TSSEL=1)
An on-board timer / counter chip 8254 is used to provide a trigger source
for A/D conversion at a fixed rate. Two counters of the 8254 chip are
cascaded together to generate trigger pulse with precise period. Please
refer to section 5.3 for 8254 architecture. This mode is ideal for high
speed A/D conversion. It can be combined with the FIFO half-full interrupt
or EOC interrupt to transfer data. It is also possible to use software FIFO
polling to transfer data. The A/D trigger, A/D data transfer and Interrupt
can be set independently. Most of the complex applications can thus be
covered.
It's recommended using this mode if your applications need a fixed and
precise A/D sampling rate.
5.1.4

A/D Data Transfer Modes

The A/D data are buffered in the FIFO memory. The FIFO size on
PCI-9113A is 1024 (1K) words. If the sampling rate is 10 KHz, the FIFO
can buffer 102.4 ms analog signal. After the FIFO is full, the lasting
coming data will be lost. The software must read out the FIFO data
before it becomes full.
Operation Theorem 27