SOYO SY-6VBA133-B User Manual page 75

BIOS Setup Utility
CHIPSET FEATURES SETUP
CHIPSET
FEATURES
DRAM Timing
SDRAM Bank
Interleave
Memory Hole
Read Around
Write
Concurrent
PCI/Host
System BIOS
Cacheable
Video RAM
Cacheable
Setting Description
Normal Choose DRAM Timing
Fast
Disabled Increase DRAM performance.
2 Way
4 Way
Disabled
15M -16M Some interface cards will map
their ROM address to this area.
If this occurs, select 15M –
16M in this field.
Disabled DRAM optimization feature:
If a memory read is addressed
Enabled
to a location whose latest write
is being held in a buffer before
being written to memory, the
read is satisfied through the
buffer contents, and the read is
not sent to the DRAM.
Disabled When disabled, CPU bus will
be occupied during the entire
PCI operation period.
Enabled
Disabled Selecting Enabled allows
caching of the system BIOS
Enabled
ROM at F0000h-FFFFFh,
resulting in better system
performance. However, if any
program writes to this memory
area, a system error may result.
Disabled
Enabled The ROM area A0000-BFFFF
is cacheable.
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SY-6VBA133-B
Note
Default
Default
Default
Default
Default
Default
Default