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CHAPTER 3
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers.
The Timings programmed into this register are dependent on the system
design. Slower rates may be required in certain system designs to support
loose layouts or slower memory.
SDRAM Cycle Length
This item allows you to select the SDRAM cycle length. The set-
tings are 2 or 3.
DRAM Clock
The chipset support synchronous and asynchronous mode
between the host clock and DIMM clock.
Host CLK (default)
66MHz
Memory Hole
In order to improve performance, certain space in memory can be
reserved for ISA cards. This memory must be mapped into the memory
space below 16 MB.
Enabled
Disabled (default)
P2C/C2P Concurrency
This item allows you to Enable or Disable the PCI to CPU, CPU to
PCI concurrency. The default setting is Enabled.
Fast R-W Turn Around
This item controls the DRAM timing. It allows the user to Enable
or Disable the fast read, write turn around. The settings are Enabled or
Disabled. The default setting is Disabled.
AWARD
DIMM clock equal to host clock
DIMM clock equal to 66MHz
Memory hole supported.
Memory hole not supported.
3-13
BIOS SETUP
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