Tektronix TDS3000C Series User Manual page 146

Appendix A: Specifications
126
Trigger
Any channel, HF REJ coupled
Any channel, LF REJ coupled
Trigger level Source
range
Any channel
External trigger
External/10 trigger
Line
SET Level TO Operates with input signals ≥45 Hz
50%, typical
Trigger level Source, DC coupled
accuracy,
Any channel
typical
External trigger
External/10 trigger
Line
Trigger holdoff 250.8 ns to 10 s
range
Logic and 1.0 division at BNC, DC Coupled, ≥10 mV/div to ≤ 1 V/div (pattern, state,
Pulse Trigger delay, width, and runt triggering)
Sensitivity,
typical
Slew Rate Same as the Edge Trigger Sensitivity specifications shown earlier in this
Trigger appendix.
Sensitivity,
typical
Logic State
Triggering
2 ns
Minimum Logic
State minimum logic time: the time that a logic state must be valid before
Time, typical
and after the clock edge to be recognized. Pattern minimum logic time:
the time that a logic pattern must be valid to be recognized. Pattern with
pulse width qualification, minimum logic time: the time that a logic pattern
must be valid to be recognized.
1.5 times the DC-coupled limit
from DC to 30 kHz, attenuates
signals above 30 kHz
1.5 times the DC-coupled limits
for frequencies above 80 kHz,
attenuates signals below 80 kHz
Sensitivity
±8 divisions from center of screen,
±8 divisions from 0 V if LF REJ
trigger coupled
±800 mV
±8 V
Fixed at the midlevel of the AC line
Sensitivity
±0.2 divisions
±20 mV
±200 mV
N/A
Pattern Pattern with pulse width
2 ns 5 ns
TDS3000C Series Oscilloscope User Manual