Memory Hole; System Bios Cacheable; Top Performance - Mach P4MST-890 Setup Manual

PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with P CI
specification.
The Choices: Enabled (default), Disabled.
Vlink mode selection
This item allows you to select Vlink mode.
The Choices: B y Auto (default), Mode 0 , Mode 1.
VLink 8X Support
This item allows you to enable or disable VLink 8X support.
The Choices: Enabled (default), Disabled.
VIA PWR Management
The Choices: Enabled (default), Disabled.

Memory Hole

You can reserv e this area of system memory for ISA adapter ROM. When this
area is reserved it cannot be cached. Check the user information of periph erals
that need to use this area of system memory fo r the memory requirements.
The Choices: Disabled (default), Enabled.

System BIOS Cacheable

Selecting the " Enabled" option allows caching of the system BIOS ROM at
F0000h-FFFFFh, which is able to improve the system perfo rmance. However,
any programs that attempts to write to this memory block will cause conflicts
and result in system errors.
The Choices: Enabled (default), Disabled.

Top Performance

The Choices: Disabled (default), Enabled.
P4MST-890
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