Sharp ER-A750 Service Manual page 56

3-3. I/O areas
The addresses from 00FE80h to 00FF7Fh are called the internal I/O
area, while those from 00FF80h to 00FFFFh the external I/O area.
The internal I/O area is a space where the control registers and
built-in ports inside the CPU are addressed.
The external I/O area is a space where the peripheral devices outside
the CPU or devices on an optional card are addressed.
00FE80h
Internal I/O area
00FF80h
MPCCS
00FFA0h
LCDCZ
00FFB0h
MCR1Z
00FFB4h
MCR2Z
00FFB8h
Reserved
00FFB9h
Reserved
00FFBAh
Reserved
00FFBBh
Not used
00FFC0h
OPCCS1
00FFD0h
OPCCS2
00FFE0h
Reserved
Not used
00FFF0h
Reserved
00FFFFh
*OPCCS1 and OPCCS2 signals are decoded inside the
OPC(Option Peripheral Controller)by the OPTCS signal
for an optional decoder signal OPTCS.
They do not exist as external signals.
*The MPCCS signal is
the base signal for de-
coding the MPCA7's
internal register, and
does not exit as the
external signal.
*LCDCZ is the chip
select signal for the
LCD controller, and
MCR1Z and MCR2Z
are those for the ER-
A7RS MCR I/F.
OPTCSZ
Fig. 4
3-4. ROM space
Fig.5 shows the ROM space. The ER-A750 uses 1MB of NOR-type
flash memory instead of conventional ROM, so that the ROS1 and
ROS2 from the MPCA7 are ORed and input into the chip enable of
the flash memory.
C00000h
(MAX512KB)
C80000h
(MAX512KB)
D00000h
DFFFFFh
3-5. VRAM & RAM space
The VRAM is the display memory of the LCD. Correspondence of the
memory address and the display content is described Section 5
Display.
100000h
(512KB)
180000h
(512KB)
200000h
RAS3
(2MB)
400000h
NOT USE
BFFFFFh
*All the decode signals in the figure are supported
by the MPCA7.
3-6. Extended I/O area
The addresses from F00000h to FFFFFFh are called an extended I/O
area. The ER-A750 uses the following addresses as the break ad-
dress register (BAR) for SSP.
•
FFFF00h FFFFFFh
7 – 26
*The low-order 32 KB
of ROS1 is mapped
ROS1
over the 0page area.
*ROS1 and ROS2 are
decoded by the MPCA7.
ROS2
*ROS3 is not supported
by the MPCA7.
*Reserved for 1PL writing
ROS3
ROM on the ER-A7RS.
Fig. 5
*The VRAM which is mo
-unted on the ER-A750
VRAM
has 32 KB of memory.
*The addresses form
180000h to 187E7FH
(approximately less
RASP
than 32 KB) are mapp-
ed over the 0page area.
*The RAS3 signal from
the MPCA7 corresponds
to 2 MB of memory from
200000h to 3FFFFFh.
*ER-03/04MB interfaces
RAS3 as the base
signal.
Fig. 6