Customer Display - Sharp ER-A750 Service Manual
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- Programming manual (40 pages) ,
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- Programming manual (40 pages)
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4-4. LCD ON controller
The LCD display is turned ON and OFF by controlling the LCD
power supply VEE through the LCDENB terminal of the SED1351.
The LCDENB is in the "L" state after resetting. Electric power is
supplied from the VEE to the LCD by setting the LCDE bit inside the
R1 register of the SED1351 to "H". This makes it possible to turn ON
the LCD display.
4-5. Back light control
The back light is turned on and off through the port P15 of the CPU.
The initial value is "L" in which the back light is OFF. Writing "H" in
the P15 turns the back light on.
4-6. Luminance and contrast adjustment
•
Luminance:
Luminance is adjusted with an inverter which has
dimming function.
•
Contrast:
Contrast is adjusted by controlling the contrast ad-
justment voltage (V0) of the LM320153.
5. Customer display
The customer display uses the same vacuum fluorescent tube
(FIP7B13) as the ER-A8DP has. The display is turned on and off by
the CKDC7.
6. Pseudo SRAM
Here is an explanation for pseudo SRAM interfaces.
6-1. CPU interface
The figure below shows a typical pseudo SRAM interface in the
ER-31X system.
VRAM
DATA
DATA
ADDRESS
ADDRESS
(other than A15)
A15
VDD
R/W
HWR-
VRAM
H8/510
74LVX00
RD-
RESET
TC51V
74F32
8512AFT
VRAM
74F08
D S
VCC Q
OE-RFSH-
etc
RFSH-
Φ
Q
R
GND
RESET
etc
MA15
MPCA7
VRAM
AS-
CE-
RASP
74LVX32
Fig. 8
6-2. Pseudo SRAM address
To use the decoding signal RASP for the pseudo SRAM, RASPE, or
the RASP enabling bit for the MPCA7, must be first enabled. When
RASPE is enabled, the pseudo SRAM is decoded by the RASP signal
as follows:
1 180000h ∼ 1FFFFFh
2 008000h ∼ 00FE7Fh (same as 180000h ∼ 187E7Fh)
In 2, the 0page mapping function of the MPCA7 is used. Approxi-
mately 30 KB from the beginning of the addresses in the pseudo
SRAM can be also accessed from the 0page space.
7. NOR-type flash memory
Here is the explanation for the interface of NOR-type flash memory.
The device is Sharp’s LH28F800SU flash memory which consists of
512 K words × 16 or 1 MB × 8, with 16 blocks of 64 KB.
In addition, the LH28F800SU is the second-generation device, which
has a number of functional blocks including page buffer, command
queue, and block status register. Taking advantage of these func-
tions will improve the performance, especially in writing data.
7-1. CPU interface
The figure below shows a typical interface for the LH28F800SU of
the ER-A750 system.
5V
DATA
DQ0 ~ DQ7
VCC
VPP
ADDRESS
A0 ~ A19
HWR-
WE#
H8/510
RD-
OE#
FYPON
LH28F
PORT5-6
WP#
800SUT
NORDY
PORT5-5
RY/BY#
RESET-
RP#
BYTE#
CE0#
ROS1-
MPCA7
3/5#
ROS2-
CE1#
GND
Fig. 9
7-2. Device control
After resetting, the device automatically enters the array read mode
and perform the same action as the usual ROM, thus requiring no
special consideration when reading data.
Data can be written at high speed by using the page buffer.
8. SSP control
The ER-A750 uses flash memory in the place of EPROM, so it is
possible to rewrite the contents of the flash memory in changing the
program. However, since the existing gate array MPCA7 is used, it is
also possible to use the conventional SSP.
8-1. Operation
Like the MPCA6, the MPCA7 adopts the break address register com-
parison method for detecting addresses. The operation of this
method is briefly explained below.
The gate array always compares the break address register (ABR)
built in the gate array, with the address bus to monitor the address
bus.
If both agree, the gate array outputs the NMI signal to the CPU,
which in turn shifts from normal handling to exception handling.
In both the MPCA6 and the MPCA7, SSP is achieved by the above
operation.
The setting of the break address register (BAR) is directly written in
the addresses from FFFF00h to FFFFFFh.
7 – 28
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