Sharp ER-A750 Service Manual page 46

4) Pin description
Pin Signal
Symbol In/Out
No. name
1 CLK CLK In
2 D4 S D4 In/Out Data bus
3 D3 S D3 In/Out Data bus
4 D5 S D5 In/Out Data bus
5 D6 S D6 In/Out Data bus
6 +5V VCC —
7 D2 S D2 In/Out Data bus
8 D7 S D7 In/Out Data bus
9 D0 S D0 In/Out Data bus
10 D1 S D1 In/Out Data bus
11 NC NC —
12 INT S INT In
13 NMI VCC —
14 HALT VCC —
15 MREQ S MRQ Out
16 IORQ S IORQ Out
17 NC NC —
18 RD S RDS Out
19 WR S WRS Out
20 BUSAK BUSAK Out
21 WAIT S WAIT In
22 BUSRQ BUSRQ In
23 RESET S RES In
24 M1 S M1 Out
25 RFSH NC —
26 GND GND —
27 A0 S A0 Out
28 A1 S A1 Out
29 A2 S A2 Out
30 A3 S A3 Out
31 A4 S A4 Out
32 A5 S A5 Out
33 NC NC —
34 A6 S A6 Out
35 A7 S A7 Out
36 A8 S A8 Out
37 A9 S A9 Out
38 A10 S A10 Out
39 NC NC —
40 A11 S A11 Out
41 A12 S A12 Out
42 A13 S A13 Out
43 A14 S A14 Out
44 A15 S A15 Out
Function
Clock
+5V
NC
Interrupt request signal
Non-maskable interrupt signal
+5V
Memory request signal
Input / Output request signal
NC
Rread signal
Write signal
Bus acknowledge signal
Wait signal
Bus request signal
Reset signal
Machine cycle one signal
NC
GND
Address bus
Address bus
Address bus
Address bus
Address bus
Address bus
NC
Address bus
Address bus
Address bus
Address bus
Address bus
NC
Address bus
Address bus
Address bus
Address bus
Address bus
2-6. Z80 CTC
1) Features
•
Four independently programmable counter/timer channels, each
with a readable downcounter and a selectable 16 or 256 pre-
scaler. Downcounters are reloaded automatically at zero count.
•
Selectable positive or negative trigger initiates timer operation.
•
Three channels have Zero Count/Timeout outputs capable of driv-
ing Darlington transistors. (1.5mV @ 1.5V)
•
NMOS version for cost sensitive performance solutions.
•
CMOS version for the designs requiring low power consumption
•
NMOS Z0843004 - 4 MHz, Z0843006 - 6.17 MHz.
•
CMOS Z84C3006 - DC to 6.17 MHz, Z84C3008 - DC to 8 MHz,
Z84C3010 - DC to 10 MHz
•
Interfaces directly to the Z80 CPU or—for baud rate generation—
to the Z80 SIO.
•
Standard Z80 Family daisy-chain interrupt structure provides fully
vectored, prioritaized interrupts without external logic. The CTC
may also be used as an interrupt controller.
•
6 MHz version supports 6.144 MHz CPU clock operation.
2) General description
The Z80 CTC, hereinafter referred to as Z80 CTC or CTC, four-chan-
nel counter/timer can be programmed by system software for a
broad range of counting and timing applications. The four indepen-
dently programmable channels of the Z80 CTC satisfy common mi-
crocomputer system requirements for event counting, interrupt and
interval timing, and general clock rate generation.
System design is simplified because the CTC connects directly to
both the Z80 CPU and the Z80 SIO with no additional logic. In larger
systems, address decoders and buffers may be required.
CPU
DATA
BUS
CTC
CONTROL
FROM
CPU
DAISY
CHAIN
INTERRUPT
CONTROL
Programming the CTC is straightforward: each channel is pro-
grammed with two bytes: a third is necessary when interrupts are
enabled. Once started, the CTC counts down, automatically reloads
its time constant, and resumes counting. Software timing loops are
completely eliminated. Interrupt processing is simplified because
only one vector need be specified: the CTC internally generates a
unique vector for each channel.
The Z80 CTC requires a single +5% V power supply and the stan-
dard Z80 single-phase system clock. It is packaged in 28-pin DIPs, a
44-pin plastic chip carrier, and a 44-pin Quad Flat Pack. (Figures 2a,
2b, and 2c). Note that the QFP package is only available for CMOS
versions.
7 – 16
D0 CLK/TRG0
D1 ZC/TO0
D2
D3 CLK/TRG1
D4 ZC/TO1
D5
D6 CLK/TRG2
D7 ZC/TO2
CE
CS0 CLK/TRG3
CS1
M1 RESET
IORQ
RD
Z80 CTC
IEI
IEO
INT
CLK +5V GND
Figure 1. Pin Functions
CHANNEL
SIGNALS