Sharp ER-A750 Service Manual page 48

2-7. PD71037
DMA CONTROLLER
The PD71037 is a direct memory access controller (DMAC) for the
micro processor system. It provides higher processing speed and
lower power consumption in comparison with those in conventional
use. Each of the four built-in DMA channels has 64-KB addresses
and the function of counting the number of bytes of transferred data,
and can transfer data from I/O to memory and from memory to
memory as well.
1) FEATURES
•
The clock speed is 10 MHz, twice that of the PD8237A-5 (clock
speed of 5 MHz).
•
Each of the four DMA channels can be operated independently.
•
Each channel can be self-initialized.
•
Data is transferrable from memory to memory.
•
Data in memory can independently initialized by block.
•
High speed data transfer:
3.2 MB/sec. (clock seed of 10 MHz, normal transfer mode)
5.0 MB/sec. (clock speed of 10 MHz, compression transfer mode)
•
The number of DMA channels can directly be expanded
(Expansion mode).
•
END input when data transfer is finished.
•
Software DMA request available.
•
CMOS
•
Low power consumption
2) Pin configuration
READY 1
HLDAK 2
ASTB 3
AEN 4
HLDRQ 5
µPD71037GB-3B4
NC 6
CS 7
CLK 8
RESET 9
DMAAK2 1 0
DMAAK3 1 1
3) Pin configuration
Pin
No.
1
2
3
4
5
6
7
8
9
10 DMAAK2
11 DMAAK3
12 DMARQ3
13 DMARQ2
14 DMARQ1
15 DMARQ0
16
17
18
19
20
21 DMAAK1
22 DMAAK0
23
24
25
26
27
28
29
33 A3
32 A2
30
31 A1
31
30 A0
32
29 VDD
33
28 NC
27 A8/D0
34
26 A9/D1
35 END / TC
25 A10/D2
36
24 A11/D3
37
23 A12/D4
38
39
40
41
42
43
44
7 – 18
Signal
Symbol In/Out
name
READY READY In
HLDAK HLDAK In
ASTB S ASTB Out
AEN S AEN Out
HLDRQ HLDRQ Out
NC NC —
CS CS In
CLK CLK In
RESET SRNRESET In
S DACK2 Out
S DACK3 Out
S DRQ3 In
S DRQ2 In
S DRQ1 In
S DRQ0 In
GND GND —
NC NC —
A15/D7 S D7 In/Out Data bus
A14/D6 S D6 In/Out Data bus
A13/D5 S D5 In/Out Data bus
S DACK1 Out
S DACK0 Out
A12/D4 S D4 In/Out Data bus
A11/D3 S D3 In/Out Data bus
A10/D2 S D2 In/Out Data bus
A9/D1 S D1 In/Out Data bus
A8/D0 S D0 In/Out Data bus
NC NC —
VDD VCC —
A0 S A0 In
A1 S A1 In
A2 S A2 In
A3 S A3 In
NC NC —
TC In/Out End / Terminal cut signal
A4 S A4 In
A5 S A5 In
A6 S A6 In
A7 S A7 In
IORD S IOR In/Out I/O read signal
IOWR S IOW In/Out I/O write signal
MRD S MRD Out
MWR NC —
NC NC —
Function
Ready signal
Hold acknowledge signal
Address strobe signal
Address enable signal
Hold request signal
NC
Chip select signal
Clock
Reset signal
DMA acknowlidge signal
DMA acknowlidge signal
DMA request signal
DMA request signal
DMA request signal
DMA request signal
GND
NC
DMA acknowlidge signal
DMA acknowlidge signal
NC
+5V
Address bus
Address bus
Address bus
Address bus
NC
Address bus
Address bus
Address bus
Address bus
Memory read signal
NC
NC