Multiword Dma Timings; Figure 25. Multiword Dma Cycle Timing Chart; Figure 26. Multiword Dma Cycle Timings - IBM IC35L040AVVN07-0 - 40GB IDE Deskstar 120GXP 7200RPM UATA-100 07N9682 Specifications

6.2.3 Multiword DMA timings

The Multiword DMA timing meets Mode 2 of the ATA/ATAPI-6 description.
CS0-/CS1-
DMARQ
DMACK-
DIOR-/DIOW-
READ DATA
WRITE DATA

Figure 25. Multiword DMA cycle timing chart

t0 Cycle time
tD DIOR–/DIOW– asserted pulse width
tE DIOR– data access
tF DIOR– data hold
tG DIOR–/DIOW– data setup
tH DIOW– data hold
tI DMACK– to –DIOR–/DIOW– setup
tJ DIOR–/DIOW– to DMACK– hold
tKR/tKW DIOR–/DIOW– negated pulse width
tLR/tLW DIOR–/DIOW– to DMARQ– delay
tM CS (1:0) valid to DIOR–/DIOW–
tN CS (1:0) hold
tZ DMACK– to read data released

Figure 26. Multiword DMA cycle timings

tM
t0
tI tD
tG
tE
tG
PARAMETER DESCRIPTION
Deskstar 120GXP hard disk drive specifications
tN
tLR/tLW
tJ
tKR/tKW
tF
tH
MIN (ns)
120
70
–
5
20
10
0
5
25
–
25
10
–
29
tZ
MAX (ns)
–
–
50
–
–
–
–
–
–
35
–
–
25