Data Register; Device Control Register; Drive Address Register; Figure 68. Device Control Register - IBM DTLA-305040 - Deskstar 41.1 GB Hard Drive Specifications

9.5 Data Register

This register is used to transfer data blocks between the device data buffer and the host. It is also the
register through which sector information is transferred on a Format Track command and configuration
information is transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers
are PIO only.
The register contains valid data only when DRQ=1 in the Status Register.

9.6 Device Control Register

Figure 68. Device Control Register

Bit Definitions
SRST (RST) Software Reset. The device is held reset when RST=1. Setting RST=0 re-enables the
device.
The host must set RST=1 and wait for at least 5us before setting RST=0 to ensure that
the device recognizes the reset.
-IEN Interrupt Enable. When -IEN=0 and the device is selected, device interrupts to the host
will be enabled. When -IEN=1 or the device is not selected, device interrupts to the host
will be disabled.

9.7 Drive Address Register

Figure 69. Drive Address Register

This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ High Impedance. This bit is not driven and will always be in a high impedance state.
-WTG -Write Gate. This bit is 0 when writing to the disk device is in progress.
Device Control Register
7 6 5
– – –
Drive Address Register
7 6 5
HIZ –WTG –H3
Deskstar 40GV & 75GXP hard disk drive specifications
4 3 2
– 1 SRST –IEN
4 3 2
–H2 –H1 –H0 –DS1
71
1 0
0
1 0
–DS0