Signal Definitions (Pata Model); Table 13: Signal Definitions - Hitachi HTS542525K9SA00 Specifications

6.2 Signal definitions (PATA model)

The pin assignments of interface signals are listed as follows:

Table 13: Signal definitions

PIN SIGNAL
01 RESET-
03 DD7
05 DD6
07 DD5
09 DD4
11 DD3
13 DD2
15 DD1
17 DD0
19 GND
21 DMARQ
23 DIOW-(*)
25 DIOR-(*)
27 IORDY-(*)
29 DMACK-
31 INTRQ
33 DA1
35 DA0
37 CS0-
39 DASP-
Notes:
O designates an output from the drive
I designates an input to the drive
I/O designates an input/output common
OD designates an Open-Drain output
The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These
lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if
the Ultra DMA transfer mode was previously chosen via Set Features. The drive becomes aware of this change
upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of
DMACK- at the termination of the DMA burst.
I/O Type
I TTL
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
O 3–state
I TTL
I TTL
O 3–state
I TTL
O 3–state
I TTL
I TTL
I TTL
I/O OD
Deskstar 7K160 Hard Disk Drive Specification
PIN SIGNAL
02 GND
04 DD08
06 DD09
08 DD10
10 DD11
12 DD12
14 DD13
16 DD14
18 DD15
(20) Key
22 GND
24 GND
26 GND
28 CSEL
30 GND
32
34 PDIAG-
36 DA02
38 CS1-
40 GND
23
I/O Type
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I/O 3–state
I TTL
I/O OD
I TTL
I TTL