Drive Address Register; Device/Head Register - Hitachi HTS542525K9SA00 Specifications

9.8 Drive Address Register

Table 52: Drive Address Register
7 6
HIZ -WTG -H3
This register contains the inverted drive select and head select addresses of the currently selected drive.
Bit Definitions
HIZ High Impedance. This bit is not a device and will always be in a high impedance state.
-WTG Write Gate. This bit is 0 when writing to the disk device is in progress.
-H3, -H2,- -Head Select. These four bits are the one's complement of the binary coded address of the cur-
H1,-H0- rently selected head. Bit -H0 is the least significant.
-DS1 Drive Select 1. The Drive Select bit for device 1 is active low. DS1 = 0 when device 1 (slave) is
selected and active.
-DS0 Drive Select 0. The Drive Select bit for device 0 is active low. DS0 = 0 when device 0 (master) is
selected and active.

9.9 Device/Head Register

Table 53: Device Head/Register
7 6
1 L
This register contains the device and head numbers.
Bit Definitions
L Binary encoded address mode select. When L = 0, addressing is by CHS mode. When L = 1,
addressing is by LBA mode.
DRV Device. When DRV = 0, device 0 (master) is selected. When DRV = 1, device 1 (Slave) is
selected.
HS3, HS2, Head Select. These four bits indicate the binary encoded address of the head. Bit HS0 is the least
HS1, HS0 significant bit. At command completion, these bits are updated to reflect the currently selected
head. The head number may be from zero to the number of heads minus one. In LBA mode, HS3
through HS0 contain bits 24–27 of the LBA. At command completion these bits are updated to
reflect the current LBA bits 24–27.
5 4 3
-H2 -H1
5 4 3
1 DRV HS3
Deskstar 7K160 Hard Disk Drive Specification
2 1 0
-H0 -DS1 -DS0
2 1 0
HS2 HS1 HS0
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