Cpu-1 - Clevo D900C Service Manual

Schematic Diagrams

CPU-1

VCORE
1.2VS
VTT_OU T_R IGHT
Sheet 3 of 40
CPU-1
VTT_OUT_LEF T
10 CPU_INIT#
VTT_OU T_LEF T
VTT_OUT_RIGHT
R83
124_1%_04
C PU_GTLR EF0_D IVID ER
R88
210_1%_06
B - 4 CPU-1
U19A
5 CPU_A#[3..16]
CPU _A#3 L5
A03#
CPU _A#4 P6
A04#
CPU _A#5 M5
A05#
CPU _A#6
L4
A06#
CPU _A#7
M4
A07#
CPU _A#8 R4
A08#
CPU _A#9 T5
A09#
CPU _A#10 U6
A10#
CPU _A#11 T4
A11#
CPU _A#12
U5
A12#
CPU _A#13 U4
A13#
CPU _A#14 V5
A14#
CPU _A#15 V4
A15#
CPU _A#16 W5
A16#
N4
RSVD
C PU_REQ#[0.. 4]
P5
5 CPU_REQ#[0..4] RSVD
C PU _REQ#0 K4
REQ0#
C PU _REQ#1 J5
REQ1#
C PU _REQ#2 M6
REQ2#
C PU _REQ#3 K6
REQ3#
C PU _REQ#4
J6
REQ4#
C PU _ADSTB0#
R6
5 CPU_ADSTB0# ADSTB0#
PEC I G5
10 PECI PC_REQ#
5 CPU_A#[17..35]
CPU _A#17 AB6
A17#
CPU _A#18 W6
A18#
CPU _A#19
Y6
VCORE 34 A19#
CPU _A#20 Y4
A20#
CPU _A#21 AA4
A21#
CPU _A#22 AD6
A22#
CPU _A#23 AA5
1.2VS 4..6,9,12,15..17,30
A23#
CPU _A#24
AB5
A24#
CPU _A#25
AC5
A25#
CPU _A#26 AB4
A26#
CPU _A#27 AF5
A27#
CPU _A#28 AF4
VTT_OR 4,34 A28#
CPU _A#29 AG6
A29#
CPU _A#30
AG4
A30#
CPU _A#31
AG5
A31#
CPU _A#32 AH4
A32#
CPU _A#33 AH5
VTT_OL 4 A33#
CPU _A#34 AJ5
A34#
CPU _A#35 AJ6
A35#
C PU_AD STB1# AD5
5 CPU_ADSTB1# ADSTB1#
C PU _ADS#
D2
5 CPU_ADS#
ADS#
C PU _BNR #
C2
5 CPU_BNR#
BNR#
C PU _HI T# D4
5 CPU_HIT# HIT#
H4
RSP#
C PU _BPRI# G8
5 CPU_BPRI# BPRI#
C PU _DBSY # B2
5 CPU_DBSY# DBSY#
VTT_OU T_R IGHT C PU _DR D Y#
C1
5 CPU_DRDY#
DRDY#
C PU _HI TM#
E4
5 CPU_HITM#
HITM#
R79 62_1%_06 C PU _IERR # AB2
IERR#
C PU _IN IT# P3
INIT#
C PU _LOCK# C3
5 CPU_LOCK# LOCK#
C123
C PU _TR DY # E3
5 CPU_TRDY#
TRDY#
AD3
BINIT#
33P_04 C PU _DEF ER # G7
5 CPU_DEFER# DEFER#
C PU _GTLR EF2 F2
EDRDY#
AB3
MCERR#
U2
AP0#
R68 62_1%_06
U3
AP1#
C PU _BR0# F3
5 CPU_BR0# BR0#
R497 51_04 TP_CPU _G1 G1
RSVD
R80 51_04 TESTH I_8 G3
TESTHI08
R76 51_04 TESTH I_9
G4
TESTHI09
R81 51_04 TESTH I_10
H5
VTT_OU T_LEF T
TESTHI10
J16
DP0#
H15
DP1#
H16
DP2#
J17
DP3#
R34 62_1%_06
VTT_OU T_R IGH T
C PU _GTLR EF0 H1
GTLREF
C PU _RST# G23
5 CPU_RST# RESET#
CPU _RS#[ 0. .2]
5 CPU_RS#[0..2]
C PU_R S#0
B3
RS0#
C PU_R S#1
F5
RS1#
C PU_R S#2 A3
RS2#
CPU LGA775-P4_21
VTT_OUT_LEFT
PLEASE COLSE TO Pin-H1
R507
124_1%_04(R)
R84 10_04 CPU_GTLR EF0
CPU_GTLREF0 4
C PU _GTLR EF2_D IVIDER
C131
C132
R511
1U_04 220P_04 210_1%_06(R)
CPU_D#[0..15] 5
B4 C PU_D#0
D00#
C5 C PU_D#1
D01#
A4 C PU_D#2
D02#
C PU_D#3
C6
D03#
C PU_D#4
A5
D04#
B6 C PU_D#5
D05#
B7 C PU_D#6
D06#
A7 C PU_D#7
D07#
A10 C PU_D#8
D08#
C PU_D#9
A11
D09#
B10 C PU_D#10
D10#
C11 C PU_D#11
D11#
D8 C PU_D#12
D12#
B12 C PU_D#13
D13#
C PU_D#14
C12
D14#
C PU_D#15
D11
D15#
A8 C PU_DBI0#
DBI0# CPU_DBI0# 5
C8 C PU _DSTBN 0#
DSTBN0# CPU_DSTBN0# 5
B9 C PU _DSTBP0#
DSTBP0# CPU_DSTBP0# 5
CPU_D#[16..31] 5
G9 C PU_D#16
D16#
F8 C PU_D#17
D17#
F9 C PU_D#18
D18#
E9 C PU_D#19
D19#
C PU_D#20 VCORE
D7
D20#
E10 C PU_D#21
D21#
D10 C PU_D#22
D22#
F11 C PU_D#23
D23#
F12 C PU_D#24
D24#
C PU_D#25 C108 C106 C99 C88
D13
D25#
C PU_D#26
E13
D26#
G13 C PU_D#27 .1U_X7R_04 .1U_X7R_04
D27#
F14 C PU_D#28 .1U_X7R_04 .1U_X7R_04
D28#
G14 C PU_D#29
D29#
F15 C PU_D#30
D30#
C PU_D#31
G15
D31#
C PU_DBI1#
G11
CPU_DBI1# 5
DBI1#
G12 C PU _DSTBN 1#
DSTBN1# CPU_DSTBN1# 5
E12 C PU _DSTBP1#
DSTBP1# CPU_DSTBP1# 5
CPU_D#[32..47] 5
C PU_D#32
G16
D32#
E15 C PU_D#33
D33#
E16 C PU_D#34
D34#
G18 C PU_D#35 VCORE
D35#
C PU_D#36
G17
D36#
C PU_D#37
F17
D37#
F18 C PU_D#38
D38#
E18 C PU_D#39
D39#
E19 C PU_D#40 C56 C498 C497 C105
D40#
F20 C PU_D#41
D41#
C PU_D#42 .1U_X7R_04 .1U_X7R_04
E21
D42#
C PU_D#43 .1U_X7R_04 .1U_X7R_04
F21
D43#
G21 C PU_D#44
D44#
E22 C PU_D#45
D45#
D22 C PU_D#46
D46#
G22 C PU_D#47
D47#
C PU_DBI2# VCORE
D19
CPU_DBI2# 5
DBI2#
G20 C PU _DSTBN 2#
DSTBN2# CPU_DSTBN2# 5
G19 C PU _DSTBP2#
DSTBP2# CPU_DSTBP2# 5
CPU_D#[48..63] 5
C PU_D#48 C47 C71
D20 + +
D48#
D17 C PU_D#49
D49#
A14 C PU_D#50 470UF/2.5V_D2(R)
D50#
C15 C PU_D#51 470UF/2.5V_D2(R)
D51#
C14 C PU_D#52
D52#
C PU_D#53
B15
D53#
C PU_D#54
C18
D54#
B16 C PU_D#55
D55#
A17 C PU_D#56
D56#
B18 C PU_D#57
D57#
C21 C PU_D#58
D58#
C PU_D#59 C59 .1U_X7R_04
B21
D59#
B19 C PU_D#60
D60#
A19 C PU_D#61 C95 .1U_X7R_04
D61#
A22 C PU_D#62
D62#
B22 C PU_D#63 C107 .1U_X7R_04
D63#
C PU _DBI3#
C20
CPU_DBI3# 5
DBI3#
C PU _DSTBN 3#
A16
CPU_DSTBN3# 5
DSTBN3#
C17 C PU _DSTBP3#
DSTBP3# CPU_DSTBP3# 5
C PU _GTLR EF2 R54 0_04(R) C PU _GTLR EF3 VTT_OUT_RIGHT
CPU_GTLREF3 4
R48
124_1%_04(R)
R75 10_04(R) C PU _GTLR EF2 C PU _GTLR EF 3_DIVID ER
C 115
C528 R47
1U_04(R ) 220P_04(R ) 210_1%_06(R)
VCORE VCORE
U19C
AA8 AH18
VCC VCC
AB8 AH19 VCORE
VCC VCC
AC23 AH21
VCC VCC U19D
AC24 AH22
VCC VCC
AC25 AH25 AM29
VCC VCC VCC
AC26 AH26 AM30
VCC VCC VCC
AC27 AH27 AM8
VCC VCC VCC
AC28 AH28 AM9
VCC VCC VCC
AC29 AH29 AN11
VCC VCC VCC
AC30 AH30 AN12
VCC VCC VCC
AC8 AH8 AN14
VCC VCC VCC
AD23 AH9 AN15
VCC VCC VCC
AD24 AJ11 AN18
VCC VCC VCC
AD25 AJ12 AN19
VCC VCC VCC
AD26 AJ14 AN21
VCC VCC VCC
AD27 AJ15 AN22
VCC VCC VCC
AD28 AJ18 AN25
VCC VCC VCC
AD29 AJ19 AN26
VCC VCC VCC
AD30 AJ21 AN29
VCC VCC VCC
AD8 AJ22 AN30
VCC VCC VCC
AE11 AJ25 AN8
VCC VCC VCC
AE12 AJ26 AN9
VCC VCC VCC
AE14 AJ8 J10
VCC VCC VCC
AE15 AJ9 J11
VCC VCC VCC
AE18 AK11 J12
VCC VCC VCC
AE19 AK12 J13
VCC VCC VCC
AE21 AK14 J14
VCC VCC VCC
AE22 AK15 J15
VCC VCC VCC
AE23 AK18 J18
VCC VCC VCC
AE9 AK19 J19
VCC VCC VCC
C93 C80
AF11 AK21 J20
VCC VCC VCC
AF12 AK22 J21
VCC VCC VCC
10U/10V_08 10U/10V_08 AF14 AK25 J22
VCC VCC VCC
AF15 AK26 J23
VCC VCC VCC
AF18 AK8 J24
VCC VCC VCC
AF19 AK9 J25
VCC VCC VCC
AF21 AL11 J26
VCC VCC VCC
AF22 AL12 J27
VCC VCC VCC
AF8 AL14 J28
VCC VCC VCC
AF9 AL15 J29
VCC VCC VCC
AG11 AL18 J30
VCC VCC VCC
AG12 AL19 J8
VCC VCC VCC
AG14 AL21 J9
VCC VCC VCC
AG15 AL22 K23
VCC VCC VCC
AG18 AL25 K24
VCC VCC VCC
AG19 AL26 K25
VCC VCC VCC
AG21 AL29 K26
VCC VCC VCC
AG22 AL30 K27
VCC VCC VCC
AG25 AL8 K28
VCC VCC VCC
AG26 AL9 K29
VCC VCC VCC
AG27 AM11 K30
VCC VCC VCC
C92 C91 AG28 AM12 K8
VCC VCC VCC
AG29 AM14 L8
VCC VCC VCC
.1U_X7R_04
AG30 AM15 M23
VCC VCC VCC
.1U_X7R_04
AG8 AM18 M24
VCC VCC VCC
AG9 AM19 M25
VCC VCC VCC
AH11 AM21 M26
VCC VCC VCC
AH12 AM22
VCC VCC
AH14 AM25
CPU LGA775-P4_21
VCC VCC
AH15 AM26
VCC VCC
CPU LGA775-P4_21
C493
C124 C98 VCORE
+ +
10U/10V_08
470UF/2.5V_D2(R)
470UF/2.5V_D2(R)
C490 C488 C486 C75
10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08
VCORE
C81 .1U_X7R_04 VCORE
C45 .1U_X7R_04
C114 .1U_X7R_04
C496 C492 C489 C487
C79 .1U_X7R_04
10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08
VCORE
C482 C481 C484 C104
10U/10V_08 10U/10V_08 10U/10V_08 10U/10V_08
R50 10_04(R) C PU _GTLR EF 3
C 110
C94
1U _04(R) 220P_04(R)
VCORE
M27
VCC
M28
VCC
M29
VCC
M30
VCC
M8
VCC
N23
VCC
N24
VCC
N25
VCC
N26
VCC
N27
VCC
N28
VCC
N29
VCC
N30
VCC
N8
VCC
P8
VCC
R8
VCC
T23
VCC
T24
VCC
T25
VCC
T26
VCC
T27
VCC
T28
VCC
T29
VCC
T30
VCC
T8
VCC
U23
VCC
U24
VCC
U25
VCC
U26
VCC
U27
VCC
U28
VCC
U29
VCC
U30
VCC
U8
VCC
V8
VCC
W23
VCC
W24
VCC
W25
VCC
W26
VCC
W27
VCC
W28
VCC
W29
VCC
W30
VCC
W8
VCC
Y23
VCC
Y24
VCC
Y25
VCC
Y26
VCC
Y27
VCC
Y28
VCC
Y29
VCC
Y30
VCC
Y8
VCC
C103 C78
10U/10V_08 10U/10V_08
C485 C483
10U/10V_08 10U/10V_08
C495 C494
10U/10V_08 10U/10V_08