Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478 CPU Specification page 29

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AC24. Write Combining (WC) Load May Result in Unintended Address on System
Bus
When the processor performs a speculative write combining (WC) load, down the path of a
Problem:
mispredicted branch, and the address happens to match a valid UnCacheable (UC) address
translation with the Data Translation Look-Aside Buffer, an unintended UnCacheable load
operation may be sent out on the system bus.
When this erratum occurs, an unintended load may be sent on system bus. Intel has only
Implication:
encountered this erratum during pre-silicon simulation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AC25. Incorrect Data May be Returned When Page Tables Are In Write Combining
(WC) Memory Space
If page directories and/or page tables are located in Write Combining (WC) memory, speculative
Problem:
loads to cacheable memory may complete with incorrect data.
Cacheable loads to memory mapped using page tables located in write combining memory may
Implication:
return incorrect data. Intel has not been able to reproduce this erratum with commercially
available software.
Workaround: Do not place page directories and/or page tables in WC memory.
For the steppings affected, see the Summary Tables of Changes.
Status:
AC26. Buffer on Resistance May Exceed Specification
The datasheet specifies the resistance range for RON (Buffer on Resistance) for the AGTL+ and
Problem:
Asynchronous GTL+ buffers as 5 to 11 Ω. Due to this erratum, RON may be as high as 13.11 Ω.
The RON value affects the voltage level of the signals when the buffer is driving the signal low.
Implication:
A higher RON may adversely affect the system's ability to meet specifications such as VIL. As
the system design also affects margin to specification, designs may or may not have sufficient
margin to function properly with an increased RON. System designers should evaluate whether a
particular system is affected by this erratum. Designs that follow the recommendations in the
®
Intel Pentium
be affected.
Workaround: No workaround is necessary for systems with margin sufficient to accept a higher RON.
For the steppings affected, see the Summary Tables of Changes.
Status:
® ®
Intel Celeron Processor in the 478-Pin Package Specification Update
® ® 850 Chipset Platform Design Guide are not expected to
4 Processor and Intel
Errata
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