Fujitsu MPG3XXXAH Product Manual page 160

Table 5.16 Ultra DMA data burst timing requirements (2 of 2)
MODE 0 MODE 1
(in ns) (in ns)
NAME
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN
t 10
AZ
t 20 20
ZAH
t 0 0
ZAD
t 20 70 20
ENV
t 75
RFS
t 160 125
RP
t 20
IORDYZ
t 0 0
ZIORDY
t 20 20
ACK
t 50 50
SS
*1: Except for some instances of t
recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before
proceeding. t is an unlimited interlock that has no maximum time value. t
UI
is a limited time-out that has a defined maximum.
*2: 80-conductor cabling shall be required in order to meet setup (t
*3: Timing for t , t , t and t
DVS DVH CVS
and STROBE) have the same capacitive load value. Due to reflections on the cable, the measurement of these timings is not valid in
a normally functioning system.
*4: For all modes the parameter t
state when not actively driven.
*5: The parameters t , and t for mode 5 is defined for a recipient at the end of the cable only in a configuration with one device at the
DS DH
end of the cable.
Note:
All timing measurement switching points (low to high and high to low) shall be taken at 1.5V.
MODE 2 MODE 3
(in ns) (in ns)
10 10 10
20 20
0 0
70 20 70 20 55
70 60 60
100 100
20 20 20
0 0
20 20
50 50
that apply to host signals only, the parameters t
MLI
shall be met for lumped capacitive loads of 15 and 40 pf at the connector where all signals (Data
CVH
may be greater than t due to the fact that the host has a pull up on IORDY- giving it a known
ZIORDY ENV
C141-E112-01EN
MODE 4
MODE 5
(in ns)
(in ns)
MAX
10 10
20 20
0 0
20 55 20 50
60 50
100 85
20 20
0 0
20 20
50 50
t and t indicate sender-to-recipient or
UI, MLI LI
is a limited time-out that has a defined minimum. t
MLI
, t ) and hold (t , t ) times in modes greater than 2.
DS CS DH CH
COMMENT
Maximum time allowed for output
drivers to release (from asserted or
negated)
Minimum delay time required for
output
Drivers to assert or negate (from
released)
Envelope time (from DMACK- to
STOP and HDMARDY- during
data in burst initiation and from
DMACK to STOP during data out
burst initiation)
Ready-to-final-STROBE time (no
STROBE edges shall be sent this
long after negation of DMARDY-)
Ready-to-pause time (that recipient
shall wait to pause after negating
DMARDY-)
Maximum time before releasing
IORDY
Minimum time before driving
IORDY (*4)
Setup and hold times for DMACK-
(before assertion or negation)
Time from STROBE edge to
negation of DMARQ or assertion
of STOP (when sender terminates
a burst)
5 - 93
LI