5.3
Protocol for command abort ................................................................................................. 5 - 73
5.4
5.5
5.6
Normal DMA data transfer................................................................................................... 5 - 77
5.7
5.8
PIO data transfer timing ....................................................................................................... 5 - 89
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
Power-on Reset Timing ........................................................................................................ 5 - 104
6.1
Response to power-on .......................................................................................................... 6 - 2
6.2
Response to hardware reset .................................................................................................. 6 - 3
6.3
Response to software reset ................................................................................................... 6 - 4
6.4
6.5
6.6
6.7
Sector slip processing ........................................................................................................... 6 - 11
6.8
6.9
Data buffer configuration ..................................................................................................... 6 - 13
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C141-E112-01EN