INTERFACE ........................................................................................................ 5 - 1
5.1
Physical Interface ................................................................................................................. 5 - 2
5.1.1
Interface signals.................................................................................................................... 5 - 2
5.1.2
5.2
Logical Interface................................................................................................................... 5 - 6
5.2.1
I/O registers .......................................................................................................................... 5 - 6
5.2.2
Command block registers ..................................................................................................... 5 - 8
5.2.3
Control block registers ......................................................................................................... 5 - 13
5.3
Host Commands ................................................................................................................... 5 - 13
5.3.1
5.3.2
Command descriptions ......................................................................................................... 5 - 16
5.3.3
Error posting......................................................................................................................... 5 - 70
5.4
Command Protocol ............................................................................................................... 5 - 71
5.4.1
5.4.2
5.4.3
Commands without data transfer .......................................................................................... 5 - 75
5.4.4
Other commands................................................................................................................... 5 - 76
5.4.5
5.5
Ultra DMA feature set .......................................................................................................... 5 - 78
5.5.1
Overview .............................................................................................................................. 5 - 78
5.5.2
Phases of operation............................................................................................................... 5 - 79
5.5.3
5.5.3.1 Initiating an Ultra DMA data in burst .................................................................................. 5 - 79
5.5.3.2 The data in transfer............................................................................................................... 5 - 80
5.5.4
5.5.4.1 Initiating an Ultra DMA data out burst ................................................................................ 5 - 83
5.5.4.2 The data out transfer............................................................................................................. 5 - 84
5.5.5
Ultra DMA CRC rules.......................................................................................................... 5 - 87
5.5.6
Series termination required for Ultra DMA.......................................................................... 5 - 88
5.6
Timing .................................................................................................................................. 5 - 89
5.6.1
PIO data transfer................................................................................................................... 5 - 89
5.6.2
Multiword data transfer ........................................................................................................ 5 - 90
C141-E112-01EN
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